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參數(shù)資料
| 型號： | AKD5394A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Super High Performance 192kHz 24-Bit ADC |
| 中文描述： | 超高性能192kHz的24位ADC |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 174K |
| 代理商： | AKD5394A |
ASAHI KASEI
[AK5394A]
MS0137-E-01
2002/07
- 5 -
14
SCLK
I/O
Serial Data Clock Pin
SDATA is clocked out on the falling edge of SCLK.
Slave mode:
SCLK requires more than 48fs clock.
Master mode:
AK5394A outputs following clocks as SCLK.
Normal Speed Mode: 128fs
Double Speed Mode: 64fs
Quad Speed Mode: 64fs
When RSTN pin = “L”, SCLK outputs “L”(normal/double speed mode) or
outputs the inverted MCLK (quad speed mode).
Serial Data Output Pin
MSB first, 2’s complement.
Frame Synchronization Signal Pin
Slave mode:
When “H”, the data bits are clocked out on SDATA. In I
2
S mode, FSYNC is
don’t care.
Master mode:
FSYNC outputs 2fs clock.
FSYNC stays “L” during reset.
Master Clock Input Pin
DFS1 DFS0 MCLK fs(typ)
L L 256fs 48kHz
L H 128fs 96kHz
H L 64fs 192kHz
H H (N/A) (N/A)
Sampling Speed Select Pin 0
DFS1 DFS0 fs(typ)
L L 48kHz
L H 96kHz
H L 192kHz
H H (N/A)
High Pass Filter Enable Pin
“L”: Disable
“H”: Enable
Sampling Speed Select Pin 1
(see #18 DFS0)
Substrate Ground Pin, 0V
Analog Ground Pin, 0V
Analog Supply Pin, 5V
Rch Analog negative input Pin
Rch Analog positive input Pin
Rch Common Voltage Pin, 2.75V
Rch Negative Reference Voltage, 1.25V
Normally connected to AGND with a large electrolytic capacitor and connected to
VREFR+ with a 0.22
μ
F ceramic capacitor.
Rch Positive Reference Voltage, 3.75V
Normally connected to AGND with a large electrolytic capacitor and connected to
VREFR- with a 0.22
μ
F ceramic capacitor.
Note: All digital inputs should not be left floating.
15
SDATA
O
16
FSYNC
I/O
17
MCLK
I
18
DFS0
I
19
HPFE
I
20
DFS1
I
21
22
23
24
25
26
BGND
AGND
VA
AINR
AINR+
VCOMR
-
-
-
I
I
O
27
VREFR
O
28
VREFR+
O
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