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參數(shù)資料
| 型號： | AKD5394A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Super High Performance 192kHz 24-Bit ADC |
| 中文描述： | 超高性能192kHz的24位ADC |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 174K |
| 代理商： | AKD5394A |
ASAHI KASEI
[AK5394A]
MS0137-E-01
2002/07
- 15 -
Offset
Calibration
1. When the capacitors of 10μF or less are connected between VREF pin and GND:
When RSTN pin goes to “L”, the digital section is powered-down. Upon returning “H”, the offset calibration cycle is
started. The offset calibration cycle should always be initiated after power-up.
During the offset calibration cycle, the digital section of the part measures and stores the values of calibration input of each
channel in registers. The calibration input value is subtracted from all future outputs. The calibration input may be obtained
from either the analog input pins (AIN+/
) or the VCOM pins depending on the state of the ZCAL pin. With ZCAL “H”,
the analog input pin voltages are measured, and with ZCAL “L”, the VCOM pin voltages are measured. The CAL output is
“H” during calibration.
2. When capacitors more than 10μF are connected between VREF pin and GND:
The distortion at low frequency can be improved by connecting large capacitors (C in Figure 5) to VREF pins. (Refer to
Figure 12) However, when the capacitors of VREF pins are larger than 10μF, it is possibility that the offset calibration does
not performed correctly if the offset calibration cycle is started right after power-up. Because the internal VREF can not
settle to the appropriate voltage when the calibration cycle is completed. In this case, the offset calibration cycle should be
started again after the VREF voltage settled. The timing is shown in Figure 6. Table 4 shows the relationship between the
capacitance and the VREF settling time.
Capacitor
C[
μ
F]
Settling Time
T[s]=5000 x C
1000
470
220
100
5
2.4
1.1
0.5
Table 4. Settling Time and capacitors connected between VREF and GND
VREFL+
1
VREFL-
2
0.22u
C
+
AK5394A
+
C
Figure 5. VREF circuit example
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