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參數(shù)資料
| 型號： | AKD5394A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Super High Performance 192kHz 24-Bit ADC |
| 中文描述： | 超高性能192kHz的24位ADC |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 174K |
| 代理商： | AKD5394A |
ASAHI KASEI
[AK5394A]
MS0137-E-01
2002/07
- 10 -
SWITCHING
CHARACTERISTICS
(Ta=25
°
C; VA=5.0V
±
5%; VD=3.0
～
5.25V; C
L
=20pF)
Parameter
Control Clock Frequency
Master Clock
Pulse width Low
Pulse width High
Serial Data Output Clock (SCLK)
Channel Select Clock (LRCK)
duty cycle
Serial Interface Timing
(Note 12)
Slave Mode (SMODE1 = “L”)
SCLK Period (Note 13)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
SCLK Pulse width Low
Pulse width High
SCLK rising to LRCK Edge (Note 14)
LRCK Edge to SCLK rising (Note 14)
LRCK Edge to SDATA MSB Valid
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Master Mode (SMODE1 = “H”)
SCLK Frequency
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
SCLK duty cycle
FSYNC Frequency
FSYNC duty cycle
SCLK falling to LRCK Edge
LRCK Edge to FSYNC rising
SCLK falling to SDATA Valid
SCLK falling to FSYNC Edge
Reset / Calibration timing
RSTN Pulse width
RSTN falling to CAL rising
RSTN rising to CAL falling (Note 15)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
RSTN rising to SDATA Valid (Note 15)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Symbol
min
typ
max
Units
fCLK
tCLKL
tCLKH
fSLK
fs
0.256
29
29
1
25
12.288
6.144
48
13.824
13.824
216
75
MHz
ns
ns
MHz
kHz
%
tSLK
tSLK
tSLK
tSLKL
tSLKH
tSLR
tLRS
tDLR
tDSS
tSF
1/128fs
1/64fs
1/64fs
33
33
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
fSLK
fSLK
fSLK
dSLK
fFSYNC
dFSYNC
tMSLR
tLRF
tDSS
tSF
20
20
128fs
64fs
64fs
50
2fs
50
1
20
20
20
Hz
Hz
Hz
%
Hz
%
ns
tSLK
ns
ns
tRTW
tRCR
tRCF
tRCF
tRCF
tRTV
tRTV
tRTV
150
8704
17408
34816
8719
17423
34831
50
ns
ns
1/fs
1/fs
1/fs
1/fs
1/fs
1/fs
Notes: 12. Refer to Serial Data Interface Section.
13. At Slave Mode, SCLK must be continuously provided more than 16fs at LRCK=“H” and “L”.
14. Specified LRCK edges not to coincide with the rising edges of SCLK.
15. The number of the LRCK rising edges after RSTN pin brought high.
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