參數(shù)資料
型號(hào)： AKD5394A
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Super High Performance 192kHz 24-Bit ADC
中文描述： 超高性能192kHz的24位ADC
文件頁(yè)數(shù)： 4/24頁(yè)
文件大小： 174K
代理商： AKD5394A
ASAHI KASEI
[AK5394A]
MS0137-E-01
2002/07
- 4 -
PIN/FUNCTION
No.
Pin Name
I/O
Function
1
VREFL+
O
Lch Positive Reference Voltage, 3.75V
Normally connected to AGND with a large electrolytic capacitor and connected to
VREFL
with a 0.22
μ
F ceramic capacitor.
Lch Negative Reference Voltage, 1.25V
Normally connected to AGND with a large electrolytic capacitor and connected to
VREFL+ with a 0.22
μ
F ceramic capacitor.
Lch Common Voltage Pin, 2.75V
Lch Analog positive input Pin
Lch Analog negative input Pin
Zero Calibration Control Pin
This pin controls the calibration reference signal.
“L” :VCOML and VCOMR
“H” : Analog Input Pins (AINL
±
, AINR
±
)
Digital Power Supply Pin, 3.3V
Digital Ground Pin, 0V
Calibration Active Signal Pin
“H” means the offset calibration cycle is in progress. Offset calibration starts
when RSTN pin goes “H”. CAL goes “L” after 8704 LRCK cycles for DFS pin =
“L”, 17408 LRCK cycles for DFS pin = “H”.
Reset Pin
When “L”, the digital section is powered-down. Upon returning “H”, an offset
calibration cycle is started. An offset calibration cycle should always be initiated
after power-up.
Serial Interface Mode Select Pin
MSB first, 2’s compliment.
SMODE2 SMODE1 MODE LRCK
L L Slave mode : MSB justified : H/L
L H Master mode : Similar to I
2
S : H/L
H L Slave mode : I
2
S : L/H
H H Master mode : I
2
S : L/H
Left/Right Channel Select Clock Pin
When RSTN pin = “L” in master mode, LRCK outputs “L”.
2
VREFL
O
3
4
5
VCOML
AINL+
AINL-
O
I
I
6
ZCAL
I
7
8
VD
DGND
-
-
9
CAL
O
10
RSTN
I
11
12
SMODE2
SMODE1
I
I
13
LRCK
I/O
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