
ASAHI KASEI
[AK4113]
MS0349-E-01
2005/03
- 10 -
SWITCHING CHARACTERISTICS (Continued)
(Ta=25
°
C; AVDD, DVDD=2.7~3.6V, TVDD=2.7~5.5V; C
L
=20pF)
Parameter
Control Interface Timing (4-wire serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
↓
” to CCLK “
↑
”
CCLK “
↑
” to CSN “
↑
”
CDTO Delay
CSN “
↑
” to CDTO Hi-Z
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 8)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive load on bus
Pulse Width of Spike Noise Suppressed by Input Filter
Reset Timing
PDN Pulse Width
Note 8. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
Note 9. I
2
C is a registered tradmark of Philips Semiconductors.
Purchase of Asahi Kasei Microsystems Co., Ltd I
2
C components conveys a license under the
Philips I
C patent to use the components in the I
2
C system, provided the system conform to the I
2
C
specifications defined by Philips.
Symbol
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
tPW
min
200
80
80
50
50
150
50
50
typ
max
45
70
400
-
-
-
-
-
-
-
0.3
0.3
-
400
50
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
pF
ns
ns
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
-
0
150