參數(shù)資料
型號: AK5701VN
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
中文描述: 16位ツヒ立體聲ADC帶鎖相環(huán)
文件頁數(shù): 44/64頁
文件大小: 747K
代理商: AK5701VN
[AK5701]
Addr
15H
Register Name
fs Select
Default
D7
HPF1
0
D6
HPF0
0
D5
D4
D3
FS3
1
D2
FS2
1
D1
FS1
1
D0
FS0
1
BCKO1
0
BCKO0
1
FS3-0: Sampling Frequency Select (
Default: “1111” (44.1kHz)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKO1-0: BCLK Output Frequency Select at Master Mode (
Table 10
)
Default: “01” (32fs)
HPF1-0: Offset Cancel HPF Cut-off Frequency and ADC Initialization Cycle (
Table 18
,
Table 30
)
Default: “00” (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
Addr
Register Name
D7
D6
16H
Clock Output Select
0
Default
0
Table 9
)
PS1-0: MCKO Output Frequency Select (
Default: “00”(256fs)
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (default)
1: Enable: Output frequency is selected by PS1-0 bits.
Table 14
)
THR: Bypass Mode (
0: OFF (default)
1: ON
Addr
Register Name
D7
D6
17H
Volume Control
0
Default
0
IVOLC: Input Digital Volume Control Mode Select
0: Independent
1: Dependent (default)
When IVOLC bit = “1”, IVL7-0 bits control both Lch and Rch volume level, while register values of IVL7-0
bits are not written to IVR7-0 bits. When IVOLC bit = “0”, IVL7-0 bits control Lch level and IVR7-0 bits
control Rch level, respectively.
Addr
Register Name
D7
D6
D5
18H
Lch Input Volume Control
IVL7
IVL6
IVL5
19H
Rch Input Volume Control
IVR7
IVR6
IVR5
Default
1
0
IVL7-0, IVR7-0: Input Digital Volume; 0.375dB step, 242 Level (
Table 29
)
Default: “91H” (0dB)
Table 5
and Table 6) and MCKI Frequency Select (
Table 11
)
D5
0
0
D4
0
0
D3
THR
0
D2
D1
PS1
0
D0
PS0
0
0
0
MCKO
0
D5
0
0
D4
0
0
D3
0
0
D2
0
0
D1
0
0
D0
0
0
IVOLC
1
D4
IVL4
IVR4
1
D3
IVL3
IVR3
0
D2
IVL2
IVR2
0
D1
IVL1
IVR1
0
D0
IVL0
IVR0
1
0
MS0404-E-02
2007/08
- 44 -
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