參數(shù)資料
型號(hào)： AK5701VN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
中文描述： 16位ツヒ立體聲ADC帶鎖相環(huán)
文件頁(yè)數(shù)： 37/64頁(yè)
文件大?。?/td> 747K
代理商： AK5701VN
[AK5701]
3.
Example of ALC Operation
Table 28
shows the examples of the ALC setting for mic recording.
fs=8kHz
Operation
4.1dBFS
Enable
16ms
fs=44.1kHz
Operation
4.1dBFS
Enable
11.6ms
Register Name
Comment
Data
01
0
00
Data
01
0
10
LMTH
ZELMN
ZTM1-0
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM1-0 bits should be the same data
as ZTM1-0 bits
Maximum gain at recovery operation
WTM1-0
00
16ms
10
11.6ms
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
ALC
E1H
+30dB
E1H
+30dB
Gain of IVOL
91H
0dB
91H
0dB
Limiter ATT step
Recovery GAIN step
ALC enable
00
00
1
1 step
1 step
Enable
00
00
1
1 step
1 step
Enable
Table 28. Example of the ALC setting
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Manual Mode
* The value of IVOL should be
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
WR (REF7-0)
WR (IVL/R7-0)
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= “1”)
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level =
4.1dBFS
ALC bit = “1”
(1) Addr=18H&19H, Data=91H
(2) Addr=1AH, Data=00H
(3) Addr=1BH, Data=E1H
ALC Operation
(4) Addr=1CH, Data=81H
Note : WR : Write
Figure 39. Registers set-up sequence at ALC operation
MS0404-E-02
2007/08
- 37 -
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