- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385095 > AK5701VN (Asahi Kasei Microsystems Co.,Ltd) 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP PDF資料下載
參數(shù)資料
| 型號(hào)： | AK5701VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ立體聲ADC帶鎖相環(huán) |
| 文件頁數(shù)： | 21/64頁 |
| 文件大小： | 747K |
| 代理商： | AK5701VN |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
[AK5701]
OPERATION OVERVIEW
■
System Clock
There are the following five clock modes to interface with external devices (
Table 1
and
Table 2
)
Mode
PLL Master Mode (
Note 25
)
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
PLL Slave Mode 2
(PLL Reference Clock: EXLRCK or EXBCLK pin)
EXT Slave Mode
EXT Master Mode (
Note 26
)
Note 25. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from the MCKO pin when MCKO bit is “1”.
Note 26. In case of EXT Master Mode, the register should be set as
Figure 49
.
Table 1. Clock Mode Setting (x: Don’t care)
PMPLL bit
1
M/S bit
1
PLL3-0 bits
See
Table 4
Figure
Figure 19
1
0
See
Table 4
Figure 20
1
0
See
Table 4
Figure 21
0
0
0
0
x
x
Figure 22
Figure 23
BCLK pin,
EXBCLK pin EXLRCK pin
BCLK pin
(Selected by
BCKO1-0 bits)
LRCK pin,
Mode
MCKO bit
MCKO pin
MCKI pin
0
L
Selected by
PLL3-0 bits
LRCK pin
(1fs) (
Note 27
)
PLL Master Mode
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
1
0
EXBCLK pin
(
≥
32fs)
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
Selected by
PLL3-0 bits
EXLRCK pin
(1fs)
1
PLL Slave Mode
(PLL Reference Clock: EXLRCK
or EXBCLK pin)
0
L
GND
EXBCLK pin
(Selected by
PLL3-0 bits)
EXBCLK pin
(
≥
32fs)
BCLK pin
(Selected by
BCKO1-0 bits)
EXLRCK pin
(1fs)
Selected by
FS1-0 bits
EXLRCK pin
(1fs)
EXT Slave Mode
0
L
Selected by
FS1-0 bits
LRCK pin
(1fs)
EXT Master Mode
0
L
Note 27. LRCK becomes 2fs at PLL Master Mode & DSP Mode 1.
Table 2. Clock pins state in Clock Mode
■
Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK5701 is power-down mode (PDN pin = “L”) and exits reset state, the AK5701 is slave mode. After exiting reset state,
the AK5701 goes to master mode by changing M/S bit = “1”.
M/S bit
Mode
0
Slave Mode
1
Master Mode
Table 3. Select Master/Salve Mode
Used pins
(default)
EXBCLK, EXLRCK
BCLK, LRCK
MS0404-E-02
2007/08
- 21 -
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK5701 | digital audio 16bit A/D converter |
| AK5702 | 4-Channel ADC with PLL & MIC-AMP |
| AK5702VN | 4-Channel ADC with PLL & MIC-AMP |
| AK6002A | Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-8 RoHS Compliant: No |
| AK6002AF | Circular Connector; No. of Contacts:23; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:16; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:16-99 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK5701VNP-L | 功能描述:IC ADC AUDIO STER 16BIT 24QFN RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Basics 標(biāo)準(zhǔn)包裝:1 系列:- 類型:電機(jī)控制 分辨率（位）:12 b 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，并聯(lián) 電壓電源:單電源 電源電壓:2.7 V ~ 3.6 V，4.5 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:100-TQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:剪切帶 (CT) 其它名稱:296-18373-1 |
| AK5702 | 制造商:AKM 制造商全稱:AKM 功能描述:portable digital audio 16bit A/D converter |
| AK5702VN | 制造商:AKM 制造商全稱:AKM 功能描述:4-Channel ADC with PLL & MIC-AMP |
| AK5703 | 制造商:AKM 制造商全稱:AKM 功能描述:4-Channel 24-bit ADC with PLL & MIC-AMP |
| AK5703EN | 制造商:AKM 制造商全稱:AKM 功能描述:4-Channel 24-bit ADC with PLL & MIC-AMP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。