參數(shù)資料
型號: AK5701_07
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
中文描述: 16位ツヒ立體聲ADC帶鎖相環(huán)
文件頁數(shù): 63/64頁
文件大?。?/td> 747K
代理商: AK5701_07
[AK5701]
REVISION HISTORY
Date (YY/MM/DD)
05/08/04
05/11/22
Revision
00
01
Reason
First Edition
Error correction
Page
8
Contents
Switching Characteristics (PLL Slave Mode)
tBCKL(min): 240ns
0.4 x tBCK
tBCKH(min): 240ns
0.4 x tBCK
PLL Slave Mode
a) Mode 1: EXBCLK or EXLRCK
MCKI
b) Mode 2: MCKI
EXBCLK or EXLRCK
ALC Operation
The sentence of “The IVL and IVR are then set to
the same value for both channels.” was deleted.
Control Sequence (MIC Recording)
Figure 51
(7) Data=01H
04H
(2) 72H&73H
12H&13H
(3) 7AH
1AH
(4) 7BH
1BH
(5) 7CH
1CH
AK5701KN was added.
(1) Ambient Temperature
AK5701VN :
30
+85
°
C
AK5701KN :
40
+85
°
C
(2) Marking
AK5701VN : “5701”
AK5701KN : “5701K”
1. Control Interface Timing(CSP pin = “L”)
(1) CSN “
” to CCLK “
CSN Edge to CCLK “
(2) CCLK “
” to CSN “
CCLK “
” to CSN Edge
2. Control Interface Timing(CSP pin = “H”)
(1) CSN “
” to CCLK “
CSN Edge to CCLK “
(2) CCLK “
” to CSN “
CCLK “
” to CSN Edge
3.
Note 22
was added.
Figure 26
Figure 29
:
ECTBCLK(32fs)/BCLK(32fs)
No of 1
st
bit in Fugure 15
31
Figure 30
Figure 33
: BCLK(64fs)
No of 1
st
bit in Fugure : 15
31
Serial Control I/F
1. CSP pin = “L”
“CSN should be set to “H” once after 16 CCLKs
for each address.” was added.
2. CSP pin = “H”
“CSN should be set to “L” once after 16 CCLKs for
each address.” was added.
25
35
57
07/08/30
02
Product
Addition
1, 3, 5,
62
Spec Addition
11
Error Correction
30
31
Spec Addition
40
MS0404-E-02
2007/08
- 63 -
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