參數(shù)資料
型號(hào): AK5701_07
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP
中文描述: 16位ツヒ立體聲ADC帶鎖相環(huán)
文件頁數(shù): 27/64頁
文件大?。?/td> 747K
代理商: AK5701_07
[AK5701]
EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”)
Figure 49
The AK5701 becomes EXT Master Mode by setting as
PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of
MCKI is selected by FS1-0 bits (
Table 12
).
. Master clock is input from the MCKI pin, the internal
MCKI Input
Frequency
256fs
1024fs
512fs
256fs
Sampling Frequency
Range
7.35kHz
48kHz
7.35kHz
13kHz
7.35kHz
26kHz
7.35kHz
48kHz
Mode
FS3-2 bits
FS1 bit
FS0 bit
0
1
2
3
0
0
1
1
0
1
0
1
x
x
x
x
(default)
Table 12. MCKI Frequency at EXT Master Mode (x: Don’t care)
MCKI should always be present whenever the ADC is in operation (PMADL bit = “1” or PMADR bit = “1”). If MCKI is
not provided, the AK5701 may draw excess current and it is not possible to operate properly because utilizes dynamic
refreshed logic internally. If MCKI is not present, the ADC should be in the power-down mode (PMADL=PMADR bits
= “0”).
AK5701
DSP or
μ
P
MCKI
BCLK
LRCK
SDTO
BCLK
LRCK
SDTI
MCKO
1fs
32fs or 64fs
MCLK
256fs, 512fs or 1024fs
Figure 23. EXT Master Mode
BCLK Output
Frequency
N/A
32fs
64fs
N/A
BCKO1 bit
BCKO0 bit
0
0
1
1
0
1
0
1
(default)
Table 13. BCLK Output Frequency at Master Mode (N/A: Not available)
MS0404-E-02
2007/08
- 27 -
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