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參數(shù)資料
| 型號： | AK5701_07 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 16-Bit ツヒ Stereo ADC with PLL & MIC-AMP |
| 中文描述： | 16位ツヒ立體聲ADC帶鎖相環(huán) |
| 文件頁數(shù)： | 23/64頁 |
| 文件大?。?/td> | 747K |
| 代理商： | AK5701_07 |
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[AK5701]
When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits
(
Table 6
).
FS3 bit
FS2 bit
Mode
FS1 bit
Sampling Frequency
Range
7.35kHz
≤
fs
≤
12kHz
12kHz < fs
≤
24kHz
FS0 bit
0
0
0
1
x
x
x
x
0
1
(default
)
2
1
x
x
x
24kHz < fs
≤
48kHz
Others
Others
N/A
(x: Don’t acre, N/A: Not available)
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
■
PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BCLK pins go to “L” and irregular frequency clock is output from the MCKO pin at MCKO bit
is “1” before the PLL goes to lock state after PMPLL bit = “0”
“1”. If MCKO bit is “0”, the MCKO pin changes to “L”
(
Table 7
).
In DSP Mode 0 and 1, BCLK and LRCK start to output corresponding to Lch data after PLL goes to lock state by setting
PMPLL bit = “0”
“1”. When MSBS and BCKP bits are “01” or “10” in DSP Mode 0 and 1, BCLK “H” time of the first
pulse becomes 1/(256fs) shorter than “H” time except for the first pulse.
When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
MCKO pin
PLL State
MCKO bit = “0”
After that PMPLL bit “0”
“1”
“L” Output
PLL Unlock (except above case)
“L” Output
BCLK pin
LRCK pin
MCKO bit = “1”
Invalid
Invalid
“L” Output
Invalid
“L” Output
Invalid
1fs Output
(
Note 30
)
PLL Lock
“L” Output
See
Table 9
See
Table 10
Note 30. LRCK becomes 2fs at DSP Mode 1.
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from the MCKO pin before the PLL goes to lock state after PMPLL bit = “0”
“1”. After that, the clock selected by
Table 9
is output from the MCKO pin when PLL is locked. ADC and DAC output
invalid data when the PLL is unlocked. For DAC, the output signal should be muted by writing “0” to DACL, DACH and
DACS bits.
MCKO pin
PLL State
MCKO bit = “0”
“L” Output
“L” Output
“L” Output
MCKO bit = “1”
Invalid
Invalid
See
Table 9
After that PMPLL bit “0”
“1”
PLL Unlock (except above case)
PLL Lock
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MS0404-E-02
2007/08
- 23 -
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