參數(shù)資料
型號(hào): AK4673
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類(lèi): Codec
英文描述: Stereo CODEC with MIC/HP-AMP and Touch Screen Controller
中文描述: 立體聲編解碼器麥克風(fēng)/惠普- AMP及觸摸屏控制器
文件頁(yè)數(shù): 59/107頁(yè)
文件大?。?/td> 1171K
代理商: AK4673
[AK4673]
MS0670-E-00
2007/09
- 59 -
Stereo Line Output (LOUT/ROUT pins)
When DACL bit is “1”, single-ended Lch/Rch signal of DAC is output from the LOUT/ROUT pins. When DACL bit is
“0”, output signal is muted and LOUT/ROUT pins output VCOM voltage. The load impedance is 10k
Ω
(min.). When the
PMLO=LOPS bits = “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by
100k
Ω
(typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at power-up/down can be
reduced by changing PMLO bit at LOPS bit = “1”. In this case, output signal line should be pulled-down to VSS1 by
20k
Ω
after AC coupled as
Figure 45
. Rise/Fall time is 300ms(max) at C=1
μ
F and AVDD=3.3V. When PMLO bit = “1”
and LOPS bit = “0”, stereo line output is in normal operation.
LOVL bit set the gain of stereo line output.
When LOM bit = “1”, DAC output signal is output to LOUT and ROUT pins as (L+R)/2 mono signal.
When LOM3 bit = “1”, the signal selected by MICL3 and MICR3 bits (LIN3/RIN3 inputs or MIC-Amp outputs) to
LOUT and ROUT pins as (L+R)/2 mono signal.
“DACL”
DAC
LOUT pin
ROUT pin
“LOVL”
Figure 44. Stereo Line Output
LOPS
PMLO
0
1
0
1
Table 50. Stereo Line Output Mode Select (x: Don’t care)
Mode
LOUT/ROUT pin
Pull-down to VSS1
Normal Operation
Fall down to VSS1
Rise up to VCOM
(default)
Power-down
Normal Operation
Power-save
Power-save
0
1
LOVL
0
1
Gain
0dB
+2dB
Output Voltage (typ)
0.6 x AVDD
0.757 x AVDD
(default)
Table 51. Stereo Line Output Volume Setting
LOUT
ROUT
1
μ
F
220
Ω
20k
Ω
Figure 45. External Circuit for Stereo Line Output (in case of using Pop Reduction Circuit)
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