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參數(shù)資料
| 型號(hào)： | AK4673 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類(lèi)： | Codec |
| 英文描述： | Stereo CODEC with MIC/HP-AMP and Touch Screen Controller |
| 中文描述： | 立體聲編解碼器麥克風(fēng)/惠普- AMP及觸摸屏控制器 |
| 文件頁(yè)數(shù)： | 101/107頁(yè) |
| 文件大?。?/td> | 1171K |
| 代理商： | AK4673 |
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[AK4673]
MS0670-E-00
2007/09
- 101 -
■
MIC Input Recording (Stereo)
FS3-0 bits
(Addr:05H, D5&D2-0)
MIC Control
(Addr:02H, D2-0)
PMADL/R bits
(Addr:00H&10H, D0)
ADC Internal
State
1,111
0,000
001
101
Power Down
Initialize Normal State Power Down
1059 / fs
(1)
(2)
(7)
ALC State
ALC Enable
ALC Disable
ALC Disable
(5)
ALC Control 1
(Addr:06H)
00H
3CH
(3)
ALC Control 2
(Addr:08H)
E1H
E1H
(4)
ALC Control 3
(Addr:0BH)
00H
00H
(8)
(6)
ALC Control 4
(Addr:07H)
07H
21H
01H
(9)
Example:
PLL Master Mode
Audio I/F Format:MSB justified (ADC & DAC)
Sampling Frequency:44.1kHz
Pre MIC AMP:+20dB
MIC Power On
ALC setting:Refer to Table 34
ALC bit=“1”
(2) Addr:02H, Data:05H
(3) Addr:06H, Data:3CH
(1) Addr:05H, Data:27H
(4) Addr:08H, Data:E1H
(5) Addr:0BH, Data:00H
(7) Addr:00H, Data:41H
Addr:10H, Data:01H
Recording
(8) Addr:00H, Data:40H
Addr:10H, Data:00H
(6) Addr:07H, Data:21H
(9) Addr:07H, Data:01H
Figure 90. MIC Input Recording Sequence
<Example>
This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to
“
Figure 35. Registers set-up sequence at ALC operation
”
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1)
Set up a sampling frequency (FS3-0 bit). When the AK4673 is PLL mode, MIC and ADC should be powered-up
in consideration of PLL lock time after a sampling frequency is changed.
(2)
Set up MIC input (Addr: 02H)
(3)
Set up Timer Select for ALC (Addr: 06H)
(4)
Set up REF value for ALC (Addr: 08H)
(5)
Set up LMTH1 and RGAIN1 bits (Addr: 0BH)
(6)
Set up LMTH0, RGAIN0, LMAT1-0 and ALC bits (Addr: 07H)
(7)
Power Up MIC and ADC: PMADL = PMADR bits = “0”
→
“1”
The initialization cycle time of ADC is 1059/fs=24ms@fs=44.1kHz.
After the ALC bit is set to “1” and MIC&ADC block is powered-up, the ALC operation starts from IVOL
default value (+30dB).
The time of offset voltage going to “0” after the ADC initialization cycle depends on both the time of analog
input pin going to the common voltage and the time constant of the offset cancel digital HPF. This time can be
shorter by using the following sequence:
At first, PMVCM and PMMP bits should set to “1”. Then, the ADC should be powered-up. The wait time to
power-up the ADC should be longer than 4 times of the time constant that is determined by the AC coupling
capacitor at analog input pin and the internal input resistance 60k(typ).
(8)
Power Down MIC and ADC: PMADL = PMADR bits = “1”
→
“0”
When the registers for the ALC operation are not changed, ALC bit may be keeping “1”. The ALC operation is
disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed
when the sampling frequency is changed, it should be done after the AK4673 goes to the manual mode (ALC bit
= “0”) or MIC&ADC block is powered-down (PMADL=PMADR bits = “0”). IVOL gain is not reset when
PMADL=PMADR bits = “0”, and then IVOL operation starts from the setting value when PMADL or PMADR
bit is changed to “1”.
(9)
ALC Disable: ALC bit = “1”
→
“0”
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AK4673EG | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP and Touch Screen Controller |
| AK4675 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/RCV/HP/SPK-AMP |
| AK4675EG | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/RCV/HP/SPK-AMP |
| AK4682 | 制造商:AKM 制造商全稱:AKM 功能描述:Multi-channel CODEC with 2Vrms Stereo Selector |
| AK4682AEQ | 功能描述:IC CODEC MULTI-CHANNEL 48LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購(gòu)買(mǎi)時(shí)間 標(biāo)準(zhǔn)包裝:1,000 |
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