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參數(shù)資料
| 型號： | AK4650 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| 中文描述： | 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 66/86頁 |
| 文件大?。?/td> | 824K |
| 代理商： | AK4650 |
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[AK4650]
MS0502-E-01
2007/04
- 66 -
2)
AC-Link Input Frame (SDATAIN)
Each AC-link frame consists of one 16bit tag phase and twelve 20bit slots used for data and control.
[Slot 0]
Slot 0 is a special time frame, and consists of 16bits. Slot 0 is also named the Tag phase. The AK4650 supports bits 15-9
and bit 3. Each bit indicates “1”=valid (normal operation) or ready, “0”=invalid (abnormal operation) or not ready. If the
first bit in the slot 0 (Bit15 = “Codec Ready”) is valid, the AK4650 is ready for normal operation. If the “Codec Ready” bit
is invalid, the following bits and remaining slots are all “0”. AC’97 controller should ignore the following bits in the slot
0 and all other slots. When the ADC sampling rate is set for less than 48kHz, then bits 12 and 11 in slot 0 (corresponds to
slot 3 and slot 4 respectively) will be 1’s when valid data is transferred in SDATAIN, and will be 0’s when no data is
transmitted.
< “On-demand” base data transaction>
For variable sample rate input, the tag bit for each input slot indicates whether valid data is present or not. Thus, even in
variable sample rate mode, the AK4650 is always the master. For SDATAIN (AK4650 to Controller), the AK4650 sets
the TAG bit. For SDATAOUT (Controller to AK4650), the AK4650 sets the SLOTREQ bit and then checks for the TAG
bit in the next frame. AK4650 expects Controller will reply TAG bit in the next frame correctly.
Bit 14 means that Slot 1 (Status Address) output is valid or invalid. And Bit 13 means that Slot 2 (Status Data) is valid or
invalid. Table 55 shows the relationship between bit 14,13 and each Status of the AK4650.
Bit 15
(Codec
Ready)
Address)
Data)
1
1
1
There is a Read Command in the previous frame.
Then both Slot 1 and Slot 2 output normal data.
If the access to non-implemented register or odd register is
requested, the AK4650 returns “valid” 7-bit register address in slot
1 and returns “valid” 0000h data in slot 2 on the next AC-link frame.
In this case, Bits 14 and 13 are “1”.
1
1
0
Prohibited or non-existing
1
0
1
Prohibited or non-existing
1
0
0
There is no Read Command in the previous frame.
Bits 19-12 and 9-0 in Slot 1 are set to “0”. And Slot 2 outputs all “0”.
Table 55. SDATAIN Slot0
Note 41. The above Read sequence is done as response for previous frames read command. That is, if the previous frame
is the Write Command, AK4650 outputs bit14 =”0”, bit13 =”0” and slot 1&2 = All”0”, if there is no SLOTREQ.
Note 42. The Bits 14 and 13 in Slot 0 is independent of the SLOTREQ Bits 11 and 10 in Slot 1 which the AK4650
supports.
Bit12 means the output of Slot 3 (PCM(ADC) Left) is valid or invalid. Bit 11 is same as bit 12. Slot 4 is all “0” regardless
of bit 11. When ADEXE1-0 bits are not “00” and SLOT bit is “1”, Tag bit corresponding to the slot set by SLOTNO1-0
bits (Slot 5=Bit 10, Slot 6=Bit 9, Slot 12=Bit 3) are fixed to “1” (valid). Bits 8-4 and 2-0 are occupied with “0”.
Bit 14
(Status
Bit 13
(Status
Status
相關(guān)PDF資料 |
PDF描述 |
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| AK4650VG | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| AK4651 | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4651VG | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4665A | 20-Bit Stereo CODEC with MIC/HP-AMP |
| AK4665AEN | 20-Bit Stereo CODEC with MIC/HP-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4650VG | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| AK4651 | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4651VG | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4664VQ | 功能描述:IC CODEC STEREO 20BIT LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標(biāo)準(zhǔn)包裝:1,000 |
| AK4665A | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP |
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