參數(shù)資料
型號： AK4650
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
中文描述： 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù)： 17/86頁
文件大小： 824K
代理商： AK4650
[AK4650]
MS0502-E-01
2007/04
- 17 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD, HVDD, DVDD, TSVDD=2.7
～
3.6V; C
L
=25pF)
Parameter
Master Clock Timing
Frequency
PLL1 pin = “L”, PLL0 pin = “L”
PLL1 pin = “H”, PLL0 pin = “L”
PLL1 pin = “H”, PLL0 pin= “H”
Duty Cycle
AC link Interface Timing
BITCLK frequency
BITCLK clock Period (Tbclk=1/Fbclk)
BIT_BLK low pulse width
BIT_BLK low pulse width
BITCLK rise time
BITCLK fall time
SYNC frequency
SYNC low pulse width
Symbol
Fmclk
Fmclk
Fmclk
Dmclk
Fbclk
Tbclk
Tclk_low
Tclk_high
Trise_clk
Tfall_clk
Fsync
Tsync_low
min
-
-
-
40
-
-
36
36
-
-
-
-
typ
24.576
3.6864
12
-
12.288
81.38
40.7
40.7
-
-
48
19.5
(240 cycle)
1.3
(16 cycle)
-
-
-
-
-
max
-
-
-
60
-
-
45
45
6
6
-
-
Units
MHz
MHz
MHz
%
MHz
ns
ns
ns
ns
ns
kHz
μ
s
(Tbclk)
μ
s
(Tbclk)
ns
ns
ns
ns
ns
SYNC high pulse width
Tsync_high
-
-
SYNC rise time
SYNC fall time
Setup time (SYNC, SDATAOUT)
Hold time (SYNC, SDATAOUT)
SDATAIN delay time from BITCLK rising
edge
SDATAIN rise time
SDATAIN fall time
SDATAOUT rise time
SDATAOUT fall time
Cold Reset
(SDATAOUT = “L”, SYNC = “L”)
RESETN active low pulse width
RESETN inactive to BITCLK delay
PLL1 pin = “L” (External clock)
PLL1 pin = “L” (X’tal oscillator)
PLL1 pin = “H”, PLL0 pin = “L”
PLL1 pin = “H”, PLL0 pin = “H”
Warm Reset Timing
SYNC active high pulse width
Trise_sync
Tfall_sync
Tsetup
Thold
Tdelay
-
-
6
6
-
-
15
14
25
-
Trise_din
Tfall_din
Trise_dout
Tfall_dout
Trst_low
Trst2clk
Trst2clk
Trst2clk
Trst2clk
Tsync_high
-
-
-
-
-
-
-
-
-
6
6
6
6
-
-
-
-
-
-
ns
ns
ns
ns
μ
s
μ
s
ms
ms
ms
μ
s
1.0
-
-
-
-
1.0
42
0.5
9.5
3.2
1.3
(16 cycle)
42
0.5
9.5
3.2
-
-
-
-
-
(Tbclk)
μ
s
ms
ms
ms
SYNC inactive to BITCLK delay
PLL1 pin = “L” (External clock)
PLL1 pin = “L” (X’tal oscillator)
PLL1 pin = “H”, PLL0 pin = “L”
PLL1 pin = “H”, PLL0 pin = “H”
AC-link Low Power Mode Timing
End of Slot 2 to BITCLK, SDATAIN Low
Activate Test Mode Timing
Setup to trailing edge of RESETN
Hold from RESETN rising edge
Rising edge of RESETN to Hi-Z
Falling edge of RESETN to “L”
Trst2clk
Tsync2clk
Tsync2clk
Tsync2clk
Ts2_pdwn
Tsetup2rst
Thold2rst
Toff
Tlow
-
-
-
-
-
-
-
-
-
1.0
-
-
50
50
μ
s
ns
ns
ns
15.0
100
-
-
ns
相關(guān)PDF資料
PDF描述
AK4650VG 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
AK4651 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4651VG 16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4665A 20-Bit Stereo CODEC with MIC/HP-AMP
AK4665AEN 20-Bit Stereo CODEC with MIC/HP-AMP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4650VG 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
AK4651 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4651VG 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP
AK4664VQ 功能描述:IC CODEC STEREO 20BIT LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標(biāo)準(zhǔn)包裝:1,000
AK4665A 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP
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