參數(shù)資料
型號(hào)： AK4650
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC
中文描述： 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁(yè)數(shù)： 61/86頁(yè)
文件大?。?/td> 824K
代理商： AK4650
[AK4650]
MS0502-E-01
2007/04
- 61 -
■
Connection with Digital AC ’97 Controller
The AK4650 communicates with its companion AC ‘97 controller via a digital serial link, “AC-link”. All digital audio
streams, and command/status information are communicated over this point to point serial interconnect. A breakout of the
signals connecting the two is shown in the following figure.
AC’97
Controller
SYNC
AK4650
BITCLK
SDATAOUT
SDATAIN
RESETN
Figure 46. Connection between AK4650 and AC ’97 controller
RESETN
BITCLK
SYNC
SDATAIN
SDATAOUT
(Input) : Control signal to reset the AK4650
(Output) : 12.288MHz clock output from the AK4650
(Input) : Control signal to synchronize the AK4650 with AC’97 controller
(Output) : Data signal input to the controller (output from the AK4650)
(Input) : Data signal output to the controller (input from the AK4650)
■
Digital Interface
The AK4650 incorporates a 5 pin digital serial interface that links it to the AC ’97 controller. AC-link is a bi-directional,
fixed rate(48kHz), serial PCM digital stream. It handles input/output audio streams and 12bit ADC results, as well as
control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each
audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. DAC and ADC
resolution of the AK4650 is 16 bit resolution. The data streams currently defined by the AC ‘97 specification include:
z
PCM Playback 2 output slots
2 channel composite PCM output stream
z
PCM Record data 2 input slots
1 channel composite PCM input stream
z
Control 2 output slots
Control register write port
z
Status 2 input slots
Control register read port
z
12bit ADC data 3 input slots
12bit ADC data input stream
SYNC, fixed at 48kHz, is derived by dividing down the serial bit clock (BITCLK) output from the AK4650. BITCLK,
fixed at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots.
AC-link serial data is transitioned on each rising edge of BITCLK. The receiver of AC-link data, the AK4650 for
outgoing data and AC ’97 controller for incoming data, samples each serial bit on the falling edges of BITCLK.
The AC-link protocol provides for a special 16-bit slot (Slot 0) wherein each bit conveys a valid tag for its corresponding
time slot within the current audio frame. A “1” in a given bit position of slot 0 indicates that the corresponding time slot
within the current audio frame has been assigned to a data stream, and contains valid data. If a slot is “Tagged” invalid, it
is the responsibility of the source of the data (the AK4650 for the input stream, AC ’97 controller for the output stream),
to stuff all bit positions with 0’s during the slot’s active time.
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