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參數(shù)資料
| 型號： | AK4650 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| 中文描述： | 16位ツヒ編解碼器麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷 |
| 文件頁數(shù)： | 63/86頁 |
| 文件大小： | 824K |
| 代理商： | AK4650 |
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[AK4650]
MS0502-E-01
2007/04
- 63 -
1)
AC-Link Audio Output Frame (SDATAOUT)
[Slot 0]
SYNC
“0”
Bit5
“1/0”
“1/0”
Slot6
Slot7
Slot5
Slot4
Slot3
Slot2
Slot1
Valid
Frame
“1/0”
Slot 1
Slot 0
SDATAIN
BITCLK
“1/0” “1/0”
“0”
“0”
“0”
Slot11
“0”
“0”
“0”
“0”
Bit15 Bit14 Bit13 Bit12 Bit11
Bit10
Bit9
Bit8
Bit4
Bit3
Bit2
Bit1
Slot8
Slot10
“0”
Bit7
Slot9
Slot12
“0”
Bit6
“0”
Bit0
1 BITCLK delay
Figure 48. Slot 0
Slot 0 consists of sixteen bits (bit 15-0). Bit 15-11 are available in the AK4650. Each bit means valid by “1” and invalid by
“0”.
Bit 15 (Valid Frame bit): Validity of the frame
“1” = At least one of bit 14-11 (slot 1-4) must be valid. Bit 10-0 are ignored.
“0” = The AK4650 ignores all following information in the frame.
Bit 14 (Slot 1 valid bit): Validity of slot 1 (command address input)
Bit 13 (Slot 2 valid bit): Validity of slot 2 (command data input)
Bit 12 (Slot 3 valid bit): Validity of slot 3 (DAC Left data input)
Bit 11 (Slot 4 valid bit): Validity of slot 4 (DAC Right data input)
If each bit is “0”, the AK4650 ignores the slot indicated by “0”. On the other hand, if each bit is “1”, the slot is valid. Bit
10-0 should be “0”. (However, when LOOP bit is “1”, loopback is operated regardless of these valid bits.)
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of
BITCLK. On the immediately following falling edge of BITCLK, the AK4650 samples the assertion of SYNC. This
falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of
BITCLK, the AC ’97 controller transitions SDATAOUT into the first bit position of slot 0 (Valid Frame bit). Each new
bit position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by the AK4650 on the
following falling edge of BITCLK. This sequence ensures that data transitions, and subsequent sample points for both
incoming and outgoing data streams are time aligned.
Data should be sent to the AK4650 with MSB first through the SDATAOUT.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4650VG | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| AK4651 | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4651VG | 16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4665A | 20-Bit Stereo CODEC with MIC/HP-AMP |
| AK4665AEN | 20-Bit Stereo CODEC with MIC/HP-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4650VG | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP & TSC |
| AK4651 | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4651VG | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit ツヒ CODEC with MIC/HP/SPK-AMP |
| AK4664VQ | 功能描述:IC CODEC STEREO 20BIT LQFP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標(biāo)準(zhǔn)包裝:1,000 |
| AK4665A | 制造商:AKM 制造商全稱:AKM 功能描述:20-Bit Stereo CODEC with MIC/HP-AMP |
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