參數(shù)資料
型號(hào)： AK4646EZ
廠商： ASAHI KASEI POWER DEVICES CORP
元件分類： 消費(fèi)家電
英文描述： Stereo CODEC with MIC/SPK-AMP
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝： 4 X 4 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, QFN-32
文件頁(yè)數(shù)： 74/78頁(yè)
文件大?。?/td> 808K
代理商： AK4646EZ
[AK4646EZ]
MS0630-E-00
2007/06
- 74 -
■
Stereo Line Output
FS3-0 bits
(Addr:05H, D5&D2-0)
OVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMLO bit
(Addr:00H, D3)
1,111
0,000
91H
91H
LOUT pin
ROUT pin
(1)
(3)
(4)
(2)
(9)
Normal Output
(6)
(5)
>300 ms
(7)
(8)
>300 ms
(10)
PMBP bit
(Addr:00H, D5)
LOPS bit
(Addr:03H, D6)
DACL bit
(Addr:02H, D4)
Example:
PLL, Master Mode
Audio I/F Format :MSB justified (ADC & DAC)
Sampling Frequency:44.1KHz
Digital Volume: 0dB
MGAIN1=SPKG1=SPKG0=BEEPL bits = “0”
(1) Addr:05H, Data:27H
(2) Addr:02H, Data:10H
(3) Addr:0AH&0DH, Data:91H
(4) Addr:03H, Data:40H
(5) Addr:00H, Data:6CH
(6) Addr:03H, Data:00H
Playback
(7) Addr:03H, Data:40H
(8) Addr:00H, Data:40H
(9) Addr:02H, Data:00H
(10) Addr:03H, Data:00H
Figure 45. Stereo Lineout Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1)
Set up the sampling frequency (FS3-0 bits). When the AK4646 is PLL mode, DAC and Stereo Line-Amp
should be powered-up in consideration of PLL lock time after the sampling frequency is changed.
(2)
Set up the path of “DAC
Stereo Line Amp”: DACL bit = “0”
“1”
(3)
Set up the output digital volume (Addr: 0AH and 0DH)
When OVOLC bit is “1” (default), OVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(4)
Enter power-save mode of Stereo Line Amp: LOPS bit = “0”
“1”
(5)
Power-up DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “0”
→
“1”
The DAC outputs invalid voltage for 67/fs = 1.52ms@fs = 44.1kHz after powered-up, then it starts outputting
normal voltage. LOUT and ROUT pins rise up to VCOM voltage after PMLO bit is changed to “1”. Rise time
is 300ms (max) at C=1
μ
F.
(6)
Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
“0”
LOPS bit should be set to “0” after LOUT and ROUT pins rise up. Stereo Line-Amp goes to normal operation
by setting LOPS bit to “0”.
(7)
Enter power-save mode of Stereo Line-Amp: LOPS bit: “0”
“1”
(8)
Power-down DAC, MIN-Amp and Stereo Line-Amp: PMDAC = PMBP = PMLO bits = “1”
→
“0”
LOUT and ROUT pins fall down to AVSS. Fall time is 300ms (max) at C=1
μ
F.
(9)
Disable the path of “DAC
Stereo Line-Amp”: DACL bit = “1”
“0”
(10)
Exit power-save mode of Stereo Line-Amp: LOPS bit = “1”
“0”
LOPS bit should be set to “0” after LOUT and ROUT pins fall down.
相關(guān)PDF資料
PDF描述
AK4646 Stereo CODEC with MIC/SPK-AMP
AK4646EN Stereo CODEC with MIC/SPK-AMP
AK4647 Stereo CODEC with MIC/HP-AMP
AK4647VN Stereo CODEC with MIC/HP-AMP
AK4648 Stereo CODEC with MIC/HP/SPK-AMP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4647 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP
AK4647VN 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP
AK4647VQ 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP
AK4648 制造商:AKM 制造商全稱:AKM 功能描述:stereo CODEC with MIC/HP/SPK amplifier
AK4648EC 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP/SPK-AMP
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