- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385093 > AK4646EZ (ASAHI KASEI POWER DEVICES CORP) Stereo CODEC with MIC/SPK-AMP PDF資料下載
參數(shù)資料
| 型號(hào)： | AK4646EZ |
| 廠商： | ASAHI KASEI POWER DEVICES CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Stereo CODEC with MIC/SPK-AMP |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC32 |
| 封裝： | 4 X 4 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 20/78頁 |
| 文件大?。?/td> | 808K |
| 代理商： | AK4646EZ |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
[AK4646EZ]
MS0630-E-00
2007/06
- 20 -
■
PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the
PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, when the AK4646 is supplied stable clocks after PLL is
powered-up (PMPLL bit = “0”
→
“1”) or when the sampling frequency is changed.
1) Setting of PLL Mode
PLL
Reference
Clock Input
Pin
0
0
0
0
0
LRCK pin
1
0
0
0
1
N/A
R and C of
VCOC pin
R[
Ω
]
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
Input
Frequency
C[F]
PLL Lock
Time
(max)
1fs
-
6.8k
-
10k
10k
10k
10k
10k
10k
10k
10k
220n
-
4.7n
10n
4.7n
10n
10n
10n
10n
10n
160ms
-
2ms
4ms
2ms
4ms
40ms
40ms
40ms
40ms
(default)
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
6
7
12
13
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
12MHz
24MHz
13.5MHz
27MHz
Others
Others
Table 4. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
2) Setting of sampling frequency in PLL Mode
When PLL2 bit is “1” (PLL reference clock input is MCKI pin), the sampling frequency is selected by FS3-0 bits as
defined in Table 5.
Mode
FS3 bit
FS2 bit
FS1 bit
0
0
0
0
1
0
0
0
2
0
0
1
3
0
0
1
4
0
1
0
5
0
1
0
6
0
1
1
7
0
1
1
10
1
0
1
11
1
0
1
14
1
1
1
15
1
1
1
Others
Others
FS0 bit
0
1
0
1
0
1
0
1
0
1
0
1
Sampling Frequency
8kHz
12kHz
16kHz
24kHz
7.35kHz
11.025kHz
14.7kHz
22.05kHz
32kHz
48kHz
29.4kHz
44.1kHz
N/A
(N/A: Not available)
(default)
Table 5. Setting of Sampling Frequency at PLL2 bit = “1” and PMPLL bit = “1” (Reference Clock = MCKI pin)
When PLL2 bit is “0” (PLL reference clock input is LRCK or BICK pin), the sampling frequency is selected by FS3 and
FS2 bits. (Table 6).
FS3 bit
FS2 bit
FS1 bit
Mode
FS0 bit
Sampling Frequency
Range
7.35kHz
≤
fs
≤
12kHz
12kHz < fs
≤
24kHz
24kHz < fs
≤
48kHz
N/A
(x: Don’t care, N/A: Not available)
0
1
2
0
0
1
0
1
0
x
x
x
x
x
x
(default)
Others
Others
Table 6. Setting of Sampling Frequency at PLL2 bit = “0” and PMPLL bit = “1” PLL Slave Mode 2
(PLL Reference: Clock: LRCK or BICK pin)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4646 | Stereo CODEC with MIC/SPK-AMP |
| AK4646EN | Stereo CODEC with MIC/SPK-AMP |
| AK4647 | Stereo CODEC with MIC/HP-AMP |
| AK4647VN | Stereo CODEC with MIC/HP-AMP |
| AK4648 | Stereo CODEC with MIC/HP/SPK-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4647 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4647VN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4647VQ | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP |
| AK4648 | 制造商:AKM 制造商全稱:AKM 功能描述:stereo CODEC with MIC/HP/SPK amplifier |
| AK4648EC | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP/SPK-AMP |