參數(shù)資料
型號(hào)： AK4643EN
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： Stereo CODEC with MIC/HP/RCV/SPK-AMP
中文描述： 立體聲編解碼器麥克風(fēng)/惠普/垃圾車/胰腎聯(lián)合移植腺苷
文件頁(yè)數(shù)： 99/104頁(yè)
文件大?。?/td> 926K
代理商： AK4643EN
ASAHI KASEI
[AK4643]
MS0476-E-01
2006/10
- 99 -
Receiver-amp Output
FS3-0 bits
(Addr:05H, D5&D2-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMLO bit
(Addr:00H, D3)
1,111
0,000
18H
28H
RCP pin
Normal Output
LOPS bit
(Addr:03H, D6)
Hi-Z
Hi-Z
RCN pin
Normal Output
Hi-Z
Hi-Z
VCOM
VCOM
(1)
(6)
(7)
(8)
(11)
(9)
DACL bit
(Addr:02H, D4)
(10)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
E1H
91H
(5)
(3)
PMMIN bit
(Addr:00H, D5)
RCV bit
(Addr:21H, D0)
(2)
(4)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
LOVL = MINL bits = “0”
8dB
(3) Addr:02H, Data:10H
(1) Addr:05H, Data:27H
(6) Addr:0AH & 0DH, Data:28H
(7) Addr:00H, Data:6CH
(8) Addr:03H, Data:00H
(9) Addr:03H, Data:40H
Playback
(10) Addr:02H, Data:00H
(11) Addr:00H, Data:40H
(5) Addr:09H & 0CH, Data:91H
(2) Addr:21H, Data:01H
(4) Addr:03H, Data:40H
Figure 88. Receiver-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4643 is PLL mode, DAC and Receiver-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC
RCV-Amp and Power-save mode”: DACL=LOPS bit = “0”
“1”
(3) Set up the input digital volume (Addr: 09H and 0CH)
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
(4) Set up the output digital volume (Addr: 0AH and 0DH).
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up, the
digital volume changes from default value (0dB) to the register setting value by the soft transition.
(5) Power Up of DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “0”
→
“1”
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2’s compliment, “0”. The DAC
output reflects the digital input data after the initialization cycle (1059/fs=24ms@fs=44.1kHz) is complete.
When PMADL or PMADR bit is “1”, the DAC does not require an initialization cycle.
(6) Exit the power-save-mode of Receiver-Amp: LOPS bit = “1”
→
“0”
(7) Enter the power-save-mode of Receiver-Amp: LOPS bit = “0”
→
“1”
(8) Disable the path of “DAC
RCV-Amp”: DACL bit = “1”
“0”
(9) Power Down DAC, MIN-Amp and Receiver-Amp: PMDAC = PMMIN = PMLO bits = “1”
→
“0”
相關(guān)PDF資料
PDF描述
AK4645EZ Stereo CODEC with MIC/HP-AMP
AK4645 Stereo CODEC with MIC/HP-AMP
AK4646EZ Stereo CODEC with MIC/SPK-AMP
AK4646 Stereo CODEC with MIC/SPK-AMP
AK4646EN Stereo CODEC with MIC/SPK-AMP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4644 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with built-in MIC/HP/RCV amplifier
AK4644EN 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP/RCV-AMP
AK4645 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP
AK4645EN 制造商:AKM 制造商全稱:AKM 功能描述:Stereo CODEC with MIC/HP-AMP
AK4645ENP-L 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
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