
ASAHI KASEI
[AK4643]
MS0476-E-01
2006/10
- 64 -
Speaker Output
Power supply for Speaker-Amp (HVDD) is 2.6V to 5.25V.
Speaker Type
Load Resistance (min)
Load Capacitance (max)
Note 23. Load impedance is total impedance of series resistance (Rseries) and piezo speaker impedance at 1kHz in Figure
61. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 10
or more series resistors
should be connected at both SPP and SPN pins, respectively.
Table 56. Speaker Type and Power Supply Range
The DAC or LIN2/RIN2/LIN3/RIN3 signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL
output. The gain is set by SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.
Dynamic Speaker
8
30pF
Piezo (Ceramic) Speaker
50
3
μ
F
Gain
Default
SPKG1-0 bits
ALC bit = “0”
+4.43dB
+6.43dB
+10.65dB
+12.65dB
Table 57. SPK-Amp Gain
ALC bit = “1”
+6.43dB
+8.43dB
+12.65dB
+14.65dB
00
01
10
11
SPK-Amp Output (DAC Input = 0dBFS)
ALC bit = “0”
(LMTH1-0 bits = “00”)
3.30Vpp
4.15Vpp (Note 47)
6.75Vpp (Note 47)
8.50Vpp (Note 47)
3.30Vpp
4.15Vpp
6.75Vpp (Note 47)
8.50Vpp (Note 47)
AVDD
HVDD
SPKG1-0 bits
ALC bit = “1”
00
01
10
11
00
01
10
11
3.11Vpp
3.92Vpp
6.37Vpp (Note 47)
8.02Vpp (Note 47)
3.11Vpp
3.92Vpp
6.37Vpp (Note 47)
8.02Vpp (Note 47)
3.3V
3.3V
5.0V
Note 47. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 4.0Vpp (HVDD=3.3V) or 6.0V (HVDD=5V) or less and output
signal is not clipped.
Table 58. SPK-Amp Output Level