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參數(shù)資料
| 型號： | AK4632VN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16-Bit ツヒ Mono CODEC with ALC & MIC/SPK/Video-AMP |
| 中文描述： | 16位ツヒALC的單聲道編解碼器 |
| 文件頁數(shù)： | 65/70頁 |
| 文件大小： | 639K |
| 代理商： | AK4632VN |
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ASAHI KASEI
[AK4632]
MS0396-E-00
2005/06
- 65 -
2. In case of using POP reduction circuit of AK4632.
FS2-0 bits
(Addr:05H,
D5,D2-0)
DVOL7-0 bits
(Addr:0AH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMAO bit
(Addr:00H, D3)
XXXX
XXXX
00011000
XXXXXXX
AOUT pin
(1)
(3)
(4)
(2)
DACA bit
(Addr:02H, D4)
(9)
Normal Output
(6)
PSAON bit
(Addr:03H, D6)
(5)
>300 ms
(7)
(8)
>300 ms
(10)
Example:
PLL, Master Mode
Audio I/F Format :DSP Mode, BCKP=MSBS= “0”
Sampling Frequency: 8kHz
Digital Volume: -8dB
MGAIN1=SPKG1=SPKG0=BEEPA=ALC1M
=ALC1A= “0”
(1) Addr:05H, Data:00H
(2) Addr:02H, Data:10H
(3) Addr:0AH, Data:28H
(4) Addr:03H, Data:40H
(5) Addr:00H, Data:4CH
(6) Addr:03H, Data:00H
Playback
(7) Addr:03H, Data:40H
(8) Addr:00H, Data:40H
(9) Addr:02H, Data:00H
(10) Addr:03H, Data:00H
Figure 54. Mono Lineout Sequence
<Example>
At first, clocks should be supplied according to
“
Clock Set Up
”
sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4632 is PLL mode, DAC and Mono Line Amp should
be powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of
“
DAC
Mono Line Amp
”
: DACA bit:
“
0
”
→
“
1
”
(3) Set up the digital volume (Addr: 0AH)
After DAC is powered-up, the digital volume changes from default value (0dB) to the register setting value by
the soft transition.
(4) Enter power-save mode of Mono Line Amp: AOPSN bit =
“
0
”
→
“
1
”
(5) Power Up of DAC and Mono Line Amp: PMDAC bit = PMAO bit =
“
0
”
→
“
1
”
AOUT pin rises up to VCOM voltage. Rise time is 200ms (max 300ms) at C=1
μ
F.
(6) Exit power-save mode of Mono Line Amp after AOUT pin rises up. : AOPSN bit =
“
1
”
→
“
0
”
Mono Line Amp goes to normal operation.
(7) Enter power-save mode of Mono Line Amp: AOPSN bit =
“
0
”
→
“
1
”
(8) Power Down of DAC and Mono Line Amp: PMDAC bit = PMAO bit =
“
1
”
→
“
0
”
AOUT pin falls down to AVSS. Fall time is 200ms (max 300ms) at C=1
μ
F.
(9) Disable the path of
“
DAC
Mono Line Amp
”
: DACA bit:
“
1
”
→
“
0
”
(10) Exit power-save mode of Mono Line Amp after AOUT pin falls down. : AOPSN bit =
“
1
”
→
“
0
”
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4633VN | 16bit mono CODEC with MIC/SPK amplifier. |
| AK4633 | 16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4640 | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4640VG | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
| AK4640VN | 16BIT CODEC WITH MIC /HP/SPK-AMPl |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4633 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4633ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:LOW COST MONO CODEC WITH SPK A |
| AK4633VN | 制造商:AKM 制造商全稱:AKM 功能描述:16bit mono CODEC with MIC/SPK amplifier. |
| AK4633VNP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:LOW COST MONO CODEC WITH SPK A |
| AK4634 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
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