
ASAHI KASEI
[AK4632]
MS0396-E-00
2005/06
- 53 -
Addr
09H
Register Name
Input PGA Control
Default
D7
0
0
D6
D5
D4
D3
D2
D1
D0
IPGA6
0
IPGA5
0
IPGA4
1
IPGA3
0
IPGA2
0
IPGA1
0
IPGA0
0
IPGA6-0: Input Analog PGA (See Table 42)
Default:
“
10H
”
(0dB)
When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is
“
1
”
and ALC1 bit is
“
0
”
.
IPGA6-0 bits should be set at 2/fs(250
μ
s@fs=8kHz) after PMMIC bit is set to
“
1
”
. IPGA gain is reset when
PMMIC bit is
“
0
”
, and then IPGA operation starts from the default value when PMMIC bit is changed to
“
1
”
.
When ALC1 bit is changed from
“
1
”
to
“
0
”
, IPGA holds the last gain value set automatically by ALC1
operation.
In a manual mode, IPGA can be set to any values in Table 42.The ZTM1-0 bits set zero crossing timeout
period when IPGA value is changed. When the control register is written from the
μ
P, the zero crossing
counter is reset and its counter starts. When the signal zero crossing or zero crossing timeout, the written value
from the
μ
P becomes valid.
DATA (HEX)
GAIN (dB)
47
+27.5
46
+27.0
45
+26.5
:
:
36
+19.0
:
:
10
+0.0
:
:
06
5.0
05
5.5
04
6.0
03
6.5
02
7.0
01
7.5
00
8.0
Table 42. Input Gain Setting
Addr
Register Name
D7
D6
0AH
Digital Volume Control
DVOL7
DVOL6
DVOL5
Default
0
0
DVOL7-0: Output Digital Volume (See Table 43)
The AK4632 has a digital output volume (256 levels, 0.5dB step, Mute). The gain can be set by the DVOL7-0
bits. The volume is included in front of a DAC block, a input data of DAC is changed from +12 to –115dB
with MUTE. This volume has a soft transition function. It takes 1061/fs (=133ms @ fs = 8kHz) or 256/fs
(=32ms @ fs = 8kHz) from 00H to FFH. Soft Transition Time is set by DVTM bit.
DVOL7-0
00H
01H
02H
18H
FDH
FEH
FFH
Table 43. Digital Volume Code Table
STEP
Default
0.5dB
D5
D4
D3
D2
D1
D0
DVOL4
1
DVOL3
1
DVOL2
0
DVOL1
0
DVOL0
0
0
Gain
+12.0dB
+11.5dB
+11.0dB
0dB
114.5dB
115.0dB
MUTE (
∞
)
Default