參數資料
型號: AK4584VQ
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 24Bit 96kHz Audio CODEC with DIT/DIR
中文描述: 24位96kHz的音頻編解碼器與動態(tài)網/迪爾
文件頁數: 35/53頁
文件大?。?/td> 351K
代理商: AK4584VQ
ASAHI KASEI
[AK
4584]
MS0118-E-00
2001/11
- 35 -
Reset and Power Down
The AK4584 has both a power-down mode for all circuits by pulling the PDN pin or a partial power-down mode that is
enabled via an internal register (see Table 22). The AK4584 should be reset once by bringing PDN pin = “L” upon
power-up.
PDN pin
L
PWDITN
x
0
x
x
x
x
x
PWVRN
x
x
0
x
x
x
x
PWADN
x
x
x
0
x
x
x
PWDAN
x
x
x
x
0
x
x
CM1-0
x
x
x
x
x
00
01
Function
All Power-down
DIT Power-down
VREF Power-down
ADC Power-down
DAC Power-down
X’tal Power-down
PLL Power-down
Register Initialization
Yes
No
No
No
No
No
No
H
Table 22. Reset & Power Down
Serial Control Interface
The internal registers may be either written or read by the 4-wire μP interface pins: CSN, CCLK, CDTI & CDTO. The data
on this interface consists of Chip address (2bits, C1/0 are fixed to “00”), Read/Write (1bit), Register address (MSB first,
5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is clocked
out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a high-to-low
transition of CSN. For read operations, the CDTO output goes to high impedance after a low-to-high transition of CSN.
The maximum speed of CCLK is 5MHz. The chip address is fixed to “00”. The access to the chip address except for “00”
is invalid. PDN pin = “L” resets the registers to their default values.
CSN
CCLK
CDTI
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
C1
C0
R/W
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CDTO
Hi-Z
Write
CDTI
C1
C0
R/W
A4
A3
A2
A1
A0
CDTO
Hi-Z
Read
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
C1 - C0 : Chip Address (Fixed to "00")
R/W : READ / WRITE ("1" : WRITE, "0" : READ)
A4 - A0 : Register Address
D7 - D0 : Control Data
Figure 17. Control I/F Timing
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