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參數(shù)資料
| 型號： | AK4584VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 24Bit 96kHz Audio CODEC with DIT/DIR |
| 中文描述： | 24位96kHz的音頻編解碼器與動態(tài)網(wǎng)/迪爾 |
| 文件頁數(shù)： | 21/53頁 |
| 文件大?。?/td> | 351K |
| 代理商： | AK4584VQ |
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ASAHI KASEI
[AK4584]
MS0118-E-00
2001/11
- 21 -
System Clock
The master clock (MCLK) is derived from either a X’tal oscillator or the recovered clock from the AK4584’s PLL. MCLK
frequency is set by ICKS1-0 bits (Table 5) for X’tal mode and external clock mode. The sampling speed (normal, double
or quad speed modes) is selected by DFS1-0 bits (Table 6). The ADC is powered down during quad speed mode.
When using a X’tal oscillator, external loading capacitors between XTI/XTO pins and DVSS are required. An external
clock can be input to the XTI pin with the XTO pin left floating. The input can accept both CMOS and AC coupled clock
sources with 40%DVDD.
In slave mode, the LRCK clock input must be synchronized with MCLK, however the phase is not critical. All external
clocks (MCLK, BICK and LRCK) must be present unless PDN pin = “L” or all parts are powered down by control register,
otherwise excessive current may be produced by the internal dynamic logic. In master mode, the master clock (MCLK)
must be provided by a X’tal oscillator, external clock or internal PLL unless PDN pin = “L”.
MCLK
Double
Mode
ICKS1
ICKS0
Normal
(DFS1-0 = “00”)
256fs
384s
512fs
768fs
(DFS1-0 = “01”)
N/A
N/A
256fs
384fs
Quad
(DFS1-0 = “10”)
N/A
N/A
128fs
192fs
0
1
2
3
0
0
1
1
0
1
0
1
Default
Table 5. Master Clock Input Frequency Select (X’tal Mode)
DFS1
0
0
1
1
DFS0
0
1
0
1
Sampling Rate
Normal Speed
Double Speed
Quad Speed
N/A
Default
Table 6. Sampling Speed
MCLK
Normal
256fs
384fs
512fs
768fs
fs=44.1kHz
11.2896MHz
16.9344MHz
22.5792MHz
33.8688MHz
MCLK
Double
128fs
192fs
256fs
384fs
fs=88.2kHz
N/A
N/A
22.5792MHz
33.8688MHz
MCLK
Quad
64fs
96fs
128fs
192fs
fs=176.4kHz
N/A
N/A
22.5792MHz
33.8688MHz
MCLK
Normal
256fs
384fs
512fs
768fs
fs=48kHz
12.288MHz
18.432MHz
24.576MHz
36.864MHz
MCLK
Double
128fs
192fs
256fs
384fs
fs=96kHz
N/A
N/A
24.576MHz
36.864MHz
MCLK
Quad
64fs
96fs
128fs
192fs
fs=192kHz
N/A
N/A
24.576MHz
36.864MHz
Table 7. Master Clock Frequencies example
* X’tal mode supports from 11.2896MHz to 24.576MHz.
* Frequencies over 24.576MHz are supported in external clock mode only.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4586 | MULTI CHANNEL AUDIO CODEC WITH DIR |
| AK4586VQ | Circular Connector; MIL SPEC:MIL-C-5015 A/B/C; Body Material:Aluminum Alloy; Series:97-3100A; No. of Contacts:4; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| AK4588 | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4588VQ | 2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4589VQ | 2/8-Channel Audio CODEC with DIR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4584VQP | 功能描述:IC STEREO CODEC 24BIT 44LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標(biāo)準(zhǔn) ADC / DAC (db):81.5 / 88 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR) |
| AK4586 | 制造商:AKM 制造商全稱:AKM 功能描述:MULTI CHANNEL AUDIO CODEC WITH DIR |
| AK4586VQ | 制造商:AKM 制造商全稱:AKM 功能描述:MULTI CHANNEL AUDIO CODEC WITH DIR |
| AK4588 | 制造商:AKM 制造商全稱:AKM 功能描述:2/8 CHANNEL AUDIO CODEC WITH DIR |
| AK4588VQ | 制造商:AKM 制造商全稱:AKM 功能描述:2/8 CHANNEL AUDIO CODEC WITH DIR |
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