
ASAHI KASEI
AKM CONFIDENTIAL
[AK4561]
Rev. 0.9
2000/09
- 43 -
In Figure 31, the last IPGA value is reflected by doing the following sequence.
WR(IPGA=60H)
→
WR(ALC = “1”)
→
WR(IPGA=00H)
→
WR(ALC = “0”)
→
WR(IPGA=60H)
Figure 31
. IPGA value during
ALC operation 2
(1) WR(ALC = “1”): Enter ALC mode from Manual mode
(2) WR(IPGA=”00”): Write IPGA=00H to control register.
The IPGA value of fact is not reflected during ALC operation.
(3) WR(ALC = “0”): Finish ALC mode and enter Manual mode
(4) WR(IPGA=60H): IPGA value is changed as between the last written value to control register (IPGA=00H) and the
IPGA value at finishing ALC operation is different value.
4. IPGA writing operation at ALC operation OFF (ALC bit = “0”)
The zero crossing detection of IPGA is done to L/R channels independently. Zero crossing timeout can be set by ZTM1-0
bits. When the control register is written from
μ
P, the zero crossing counter for L/R channels commonly is reset and its
counter starts. When the signal detects zero crossing or zero crossing timeout, the written value from
μ
P becomes a valid
for the first time.
In case of writing to the control register continually, the control register should be written by an interval more than zero
crossing timeout. If an appointed interval is written, there is possible to the different value the IPGA value of L/R
channels. For example, when the present IPGA value is updated by zero crossing detection in a channel of one side and
other channel is not updated, if the new data is written in IPGA, the updated channel is keeping the last IPGA value and
other channel is updated to a new IPGA value by the last zero crossing counter. Therefore, zero crossing counter does not
reset when the zero crossing detection is waiting.
If the written value is the same as the current value, the writing value is ignored.
Control Register
Internal IPGAValue
Internal State
ALC
operation
Manual Mode
Manual Mode
60H
60H--> 40H
60H
00H
(1)
(2)
(3)
(4)
60H
60H