參數(shù)資料
型號(hào): AK4561VQ
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16bit CODEC with built-in ALC and MIC/HP-Amp
中文描述: 16位編解碼器在ALC和內(nèi)置麥克風(fēng)/惠普放大器
文件頁數(shù): 16/48頁
文件大?。?/td> 332K
代理商: AK4561VQ
ASAHI KASEI
AKM CONFIDENTIAL
[AK4561]
Rev. 0.9
2000/09
- 16 -
n
Audio Interface Format
Data is shifted in/out the SDTI/SDTO pins using BCLK and LRCK inputs. The serial data is MSB-first, 2's compliment
format, ADC is MSB justified and DAC is LSB justified.
LRCK
BCLK(I:32fs)
SDTO(o)
SDTI(i)
0
1
2
8
9
10
12
13
15
0
1
2
8
9
10
12
13
15
0
15
1
14
4
8
7
6
0
3
2
11
14
1
5
15 14
4
8
7
6
0
3
2
1
5
14
11
15
13
BCLK(I:64fs)
SDTO(o)
0
1
2
3
14
15
17
18
31
0
1
2
14
15
17
18
31
0
15
1
14
0
15 14
1
2
1
15
SDTI(i)
1
0
15
14
1
0
15
14
15:MSB, 0:LSB
Lch Data
Rch Data
Don’t Care
2
1
13
Don’t Care
16
0
16
3
13
3
13
13
3
Figure 7. Audio Data Timing
n
Control Register Timing
The data on the 3-wire serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first,
8bit). The Transmitting data is output to each bit by “
” of CCLK, the receiving data is latched by “
” of CCLK. Writing
data becomes effective by “
” of CS . CS should be held to “H” at no access.
CCLK always need 16 edges of “
” during CS = “L” Address except 00H
0BH are inhibited.
Writing of the control registers are invalid when op2-0 bits are except “111”.
Figure 8. Control Data Timing
CS
CCLK
op0-op2: Op-code (Fixed to "111:WRITE")
A0-A4:
Address
D0-D7:
Control Data
1
0
3
4
5
6
7
9
10
11
12
13
14
15
2
8
CDTI
D7
D6
D5
D4
D3
D2
D1
A4
A3
A2
A1
A0
op1
"1" "1"
op0
"1"
op2
D0
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