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參數(shù)資料
| 型號(hào)： | AK4561VQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 16bit CODEC with built-in ALC and MIC/HP-Amp |
| 中文描述： | 16位編解碼器在ALC和內(nèi)置麥克風(fēng)/惠普放大器 |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 332K |
| 代理商： | AK4561VQ |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4561]
Rev. 0.9
2000/09
- 22 -
Timer
Select
Addr
04H
Register Name
Timer Select
RESET
LTM1-0: ALC limiter operation period at zero crossing disable (ZELM = “0”)
The IPGA value is changed immediately. When the IPGA value is changed continuously, the
change is done by the period specified by LTM1-0 bits.
ALC Limiter Operation Period
LTM1
LTM0
D7
D6
D5
D4
D3
D2
D1
D0
FDTM1
1
FDTM0
0
ZTM1
1
ZTM0
0
WTM1
1
WTM0
0
LTM1
0
LTM0
0
48kz
21
μ
s
42
μ
s
83
μ
s
167
μ
s
44.1kHz
23
μ
s
45
μ
s
91
μ
s
181
μ
s
32kHz
31
μ
s
63
μ
s
125
μ
s
250
μ
s
0
0
1
1
0
1
0
1
1/fs
2/fs
4/fs
8/fs
RESET
Table 6. ALC Limiter Operation Period at zero crossing disable (ZELM = “0”)
WTM1-0: ALC Recovery Waiting Period
A period of recovery operation when any limiter operation does not occur during ALC operation.
Recovery operation is done at period set by WTM1-0 bits.
When the input signal level exceeds auto recovery waiting counter reset level set by LMTH bit,
the auto recovery waiting counter is reset.
The waiting timer starts when the input signal level becomes below the auto recovery waiting
counter reset level.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
WTM1
WTM0
0
0
0
1
1
0
1
1
Table 7. ALC Recovery Operation Waiting Period
Period
16.0ms
32.0ms
64.0ms
128.0ms
RESET
ZTM1-0: Zero crossing timeout at writing operation by
μ
P and ALC recovery operation and the zero crossing enable
(ZELM= “1”) of the ALC operation
When IPGA of each L/R channels do zero crossing or timeout independently, the IPGA value is
changed by
μ
P WRITE operation or ALC recovery operation or ALC limiter operation (ZELM =
“1”).
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
ZTM1
ZTM0
0
0
0
1
1
0
1
1
Table 8. Zero Crossing Timeout
Period
16.0ms
32.0ms
64.0ms
128.0ms
RESET
FDTM1-0: FADEIN/OUT Cycle Setting
The FADEIN/OUT operation is done by a period set by FDTM1-0 bits when FDIN or FDOUT
bits are set to “1”. When IPGA of each L/R channel do zero crossing or timeout independently,
the IPGA value is changed.
These periods are value at fs=32kHz (FS bit = “0”) or fs=48kHz (FS bit = “1”).
FDTM1
FDTM0
Period
0
0
16.0ms
0
1
32.0ms
1
0
64.0ms
1
1
128.0ms
Table 9. FADEIN/OUT Period
RESET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4562 | LOW POWER 20BIT CODEC WITH PGA |
| AK4562VN | LOW POWER 20BIT CODEC WITH PGA |
| AK4563A | Low Power 16bit 4ch ADC & 2ch DAC with ALC |
| AK4563AVF | Low Power 16bit 4ch ADC & 2ch DAC with ALC |
| AK4564 | 16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP |
相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AK4562 | 制造商:AKM 制造商全稱:AKM 功能描述:EVALUATION BOARD REV.A FOR AK4562 |
| AK4562VN | 制造商:AKM 制造商全稱:AKM 功能描述:LOW POWER 20BIT CODEC WITH PGA |
| AK4563A | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 16bit 4ch ADC & 2ch DAC with ALC |
| AK4563AVF | 制造商:AKM 制造商全稱:AKM 功能描述:Low Power 16bit 4ch ADC & 2ch DAC with ALC |
| AK4564 | 制造商:AKM 制造商全稱:AKM 功能描述:16BIT CODEC WITH BUILT-IN ALC AND MIC/HP/SPK-AMP |
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