參數(shù)資料
型號(hào)： AK4560AVQ
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 16bit CODEC with ALC and MIC/HP/SPK-Amps
中文描述： 16位編解碼器ALC和麥克風(fēng)/惠普/胰腎聯(lián)合移植，放大器
文件頁(yè)數(shù)： 16/47頁(yè)
文件大小： 339K
代理商： AK4560AVQ
ASAHI KASEI
[AK4560A]
MS0028-E-00
2000/05
- 16 -
n
Audio Interface Format
Data is shifted in/out the SDTI/SDTO pins using BCLK and LRCK inputs. The serial data is MSB-first, 2's compliment
format, ADC is MSB justified and DAC is LSB justified.
LRCK
BCLK(32fs)
SDTO(o)
SDTI(i)
0
1
2
8
9
10
12
13
15
0
1
2
8
9
10
12
13
15
0
15
1
14
4
8
7
6
0
3
2
11
14
1
5
15 14
4
8
7
6
0
3
2
1
5
14
11
15
13
BCLK(64fs)
SDTO(o)
0
1
2
3
14
15
17
18
31
0
1
2
14
15
17
18
31
0
15
1
14
0
15 14
1
2
1
15
SDTI(i)
1
0
15
14
1
0
15
14
15:MSB, 0:LSB
Lch Data
Rch Data
Don’t Care
2
1
13
Don’t Care
16
0
16
3
13
3
13
13
3
Figure 8. Audio Data Timing
n
Control Register Timing
The data on the 3-wire serial interface consists of op-code (3bit), address (LSB-first, 5bit) and control data (LSB-first,
8bit). The Transmitting data is output to each bit by “
↓
” of CCLK, the receiving data is latched by “
↑
” of CCLK. Writing
data becomes effective by “
↑
” of CS . Reading data becomes Hi-z (floating) by “
↑
” of CS . CS should be held to “H”
at no access.
CCLK always need 16 edges of “
↑
” during CS . Reading/Writing of the address except 00H
～
09H are inhibited.
Reading/Writing of the control registers by except op1-0 = “11” are invalid.
In case of reading data, nothing is written to D0
～
D7 data.
Figure 9. Control Data Timing
CS
CCLK
op0-op2: Op-code (111:WRITE, 110:READ)
A0-A4:
Address
D0-D7:
Control Data
1
0
3
4
5
6
7
9
10
11
12
13
14
15
2
8
CDTIO
D7
D6
D5
D4
D3
D2
D1
A4
A3
A2
A1
A0
op1
"1" "X"
op0
"1"
op2
D0
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