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參數(shù)資料
| 型號： | AK4533 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Audio Codec with Touch Screen Controller |
| 中文描述： | 音頻編解碼器與觸摸屏控制器 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大小： | 473K |
| 代理商： | AK4533 |
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[ASAHI KASEI]
<Revision 0.9a>
July 00
19
Table 2
shows the control registers. (See "
Touch Screen Control Register
" for the detail of 07h register)
Note that MCLK should be present when a register is accessed.
Addr
00
01
02
03
04
05
D7
AGC
LSTEP1
X
X
Mute
MSEL
D6
X
D5
X
X
D4
X
X
D3
X
D2
X
D1
TH1
RWT1
IPGA1
REF1
M1
DALPD
D0
TH0
RWT0
IPGA0
REF0
M0
ADPD
Default
03
01
10
36
00
07
AGC Control
Limit/Recovery Control
IPGA Control
Recovery Reference Level
DATT Control
Audio Powerdown &
Clock Control
Reserve
Touch Screen Control
(The value of the registers is cleared and is set to default value when PDB pin or RESETB is set to "L".)
LSTEP0
IPGA6
REF6
X
X
RSTEP1
IPGA3
REF3
M3
X
RSTEP0
IPGA2
REF2
M2
DARPD
IPGA5
REF5
X
X
IPGA4
REF4
X
X
06
07
X
X
X
X
X
X
X
D3
X
D2
X
D1
X
D0
00
80
TSPD
PW
Table 2. The AK4533 Register Map
AGC Control
When AGC bit is set to "0", AGC operation is inhibited. IPGA can be changed by writing to IPGA Control Register directly if AGC bit
is "0". When AGC bit is set to "1", AGC function is activated.
Before AGC operation, related registers, 00h - 03h, and MSEL (05h), should be set to appropriate value. (TH1/TH0 bits and AGC bit
can be set at the same time.)
Note that MSEL bit must be changed under power-down state (D0, D1, and D2 is set to "1")
When AGC operation starts, the AK4533 uses the value of IPGA Control Register as initial value. After that, IPGA value is updated
automatically. When the read of 02h register is executed, the AK4533 outputs the value which is updated by AGC circuit. Note that the
value is not the same as the value that was stored at the start of AGC operation. The write operation to 02h register is ignored.
When ADC is set to power-down mode (ADPD="1"), 00h - 03h registers are set to default values. After power-down mode is cleared
(ADPD = "0"), the write to the register is enabled. The period (516Ts@ MSEL="1", 260TS@MSEL=“0”) is required until VREFAD
is stable. The write to the registers is possible in this initial period, but AGC function is disabled for this period. The AK4533 initiates
AGC operation automatically after the end of the period.
Addr = 00h
AGC:
AGC Operation Enable
(0: Disable
1: Enable)
“1”: AGC Operation ”0”: Gain can be changed directly through A/T I/F
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| AK4534VN | 16Bit CODEC with MIC/HP/SPK-AMP |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AK4534 | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit CODEC with MIC/HP/SPK-AMP |
| AK4534VN | 制造商:AKM 制造商全稱:AKM 功能描述:16Bit CODEC with MIC/HP/SPK-AMP |
| AK4534VQ | 功能描述:IC CODEC 16BIT MIC/HP/SPK-AMP 制造商:akm semiconductor inc. 系列:* 零件狀態(tài):上次購買時間 標準包裝:1,000 |
| AK4536 | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
| AK4536VN | 制造商:AKM 制造商全稱:AKM 功能描述:16-Bit Mono CODEC with ALC & MIC/SPK-AMP |
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