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參數(shù)資料
| 型號： | AK4529 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | High Performance Multi-channel Audio CODEC |
| 中文描述： | 高性能多通道音頻解碼器 |
| 文件頁數(shù)： | 23/38頁 |
| 文件大小： | 398K |
| 代理商： | AK4529 |
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ASAHI KASEI
[AK4529]
MS0082-E-00
2001/3
- 23 -
n
Power-Down
The ADC and DACs of AK4529 are placed in the power-down mode by bringing PDN “L” and both digital filters are
reset at the same time. PDN “L” also reset the control registers to their default values. In the power-down mode, the
analog outputs go to VCOM voltage and DZF1-2 pins go to “L”. This reset should always be done after power-up. In case
of the ADC, an analog initialization cycle starts after exiting the power-down mode. Therefore, the output data, SDTO
becomes available after 522 cycles of LRCK clock. In case of the DAC, an analog initialization cycle starts after exiting
the power-down mode. The analog outputs are VCOM voltage during the initialization. Figure 10 shows the power-up
sequence.
The ADC and DACs can be powered-down individually by PWADN and PWDAN bits. In this case, the internal register
values are not initialized. When PWADN = “0”, SDTO goes to “L”. When PWDAN = “0”, the analog outputs go to
VCOM voltage and DZF1-2 pins go to “H”. Because some click noise occurs, the analog output should muted externally
if the click noise influences system application.
ADC Internal
State
PDN
522/fs
Normal Operation
Power-down
Init Cycle
Normal Operation
(1)
Don’t care
GD
GD
MCLK,LRCK,SCLK
ADC In
(Analog)
“0”data
ADC Out
(Digital)
Normal Operation
Power-down
Normal Operation
DAC Internal
State
“0”data
DAC In
(Digital)
DAC Out
(Analog)
GD
External
Mute
Mute ON
GD
(3)
(3)
(4)
(5)
(6)
(6)
(9)
516/fs
Init Cycle
(2)
DZF1/DZF2
(7)
(8)
10
～
11/fs (10)
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group delay
(GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the click
noise influences system application.
(6) Click noise occurs at the falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks (MCLK, BICK and LRCK) are stopped, the AK4529 should be in the power-down mode.
(8) DZF pins are “L” in the power-down mode (PDN = “L”).
(9) Please mute the analog output externally if the click noise (6) influences system application.
(10) DZF= “L” for 10
～
11/fs after PDN= “
↑
”.
Figure 10. Power-down/up sequence example
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