參數(shù)資料
型號: AK4396VF
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC
中文描述: 先進的多位192kHz的24位數(shù)模轉(zhuǎn)換器ツヒ
文件頁數(shù): 6/38頁
文件大?。?/td> 435K
代理商: AK4396VF
ASAHI KASEI
[AK4396]
MS0336-E-00
2004/08
- 6 -
PIN/FUNCTION
No. Pin Name
1
DVSS
2
DVDD
3
MCLK
I/O
-
-
I
Function
Digital Ground Pin
Digital Power Supply Pin, 3.3V or 5.0V
Master Clock Input Pin
Power-Down Mode Pin
When at “L”, the AK4396 is in power-down mode and is held in reset.
The AK4396 should always be reset upon power-up.
Audio Serial Data Clock Pin in PCM mode
DSD Clock Pin in DSD mode
Audio Serial Data Input Pin in PCM mode
DSD Lch Data Input Pin in DSD mode
L/R Clock Pin in PCM mode
DSD Rch Data Input Pin in DSD mode
Soft Mute Pin in parallel mode
When this pin goes “H”, soft mute cycle is initiated.
When returning “L”, the output mute releases.
Chip Select Pin in serial mode
Sampling Speed Mode Select Pin in parallel mode (Internal pull-down pin)
Chip Address 0 Pin in serial mode (Internal pull-down pin)
De-emphasis Enable 0 Pin in parallel mode
Control Data Clock Pin in serial mode
De-emphasis Enable 1 Pin in parallel mode
Control Data Input Pin in serial mode
Digital Input Format 0 Pin in PCM mode
DSD Clock Pin in DSD mode
Digital Input Format 1 Pin in PCM mode
DSD Lch Data Input Pin in DSD mode
Digital Input Format 2 Pin in PCM mode
DSD Rch Data Input Pin in DSD mode
4
PDN
I
BICK
DCLK
SDATA
DSDL
LRCK
DSDR
I
I
I
I
I
I
5
6
7
SMUTE
I
8
CSN
DFS0
CAD0
DEM0
CCLK
DEM1
CDTI
DIF0
DCLK
DIF1
DSDL
DIF2
DSDR
I
I
I
I
I
I
I
I
I
I
I
I
I
9
10
11
12
13
14
Note: All input pins except internal pull-up/down pins should not be left floating.
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