參數(shù)資料
型號(hào)： AK4396VF
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC
中文描述： 先進(jìn)的多位192kHz的24位數(shù)模轉(zhuǎn)換器ツヒ
文件頁(yè)數(shù)： 25/38頁(yè)
文件大小： 435K
代理商： AK4396VF
ASAHI KASEI
[AK4396]
MS0336-E-00
2004/08
- 25 -
Power-Down
The AK4396 is placed in the power-down mode by bringing PDN pin “L” and the anlog outputs are floating (Hi-Z).
Figure 9 shows an example of the system timing at the power-down and power-up.
PDN
Normal Operation
Internal
State
Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK, BICK, LRCK
(1)
(3)
(6)
DZFL/DZFR
External
MUTE
(5)
(3)
(1)
Mute ON
(2)
(4)
Don’t care
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge (“
↑
↓
”) of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN pin = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (PDN pin = “L”).
Other:
After exiting power-down mode (PDN pin: “L”
“H”), AOUT pins go to VCOM voltage (VA/2). This time is set
by a capacitor connected to VCOM pin and the internal resistor of VCOM pin.
E.g. C = 10
μ
F
1
τ
(typ) = 10
μ
F x 0.75k
= 7.5ms, 5
τ
(typ) = 37.5ms
1
τ
(max) = 10
μ
F x 0.975k
= 9.75ms, 5
τ
(max) = 48.75ms
Figure 9. Power-down/up sequence example
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