參數(shù)資料
型號： AK4396VF
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Advanced Multi-Bit 192kHz 24-Bit ツヒ DAC
中文描述： 先進(jìn)的多位192kHz的24位數(shù)模轉(zhuǎn)換器ツヒ
文件頁數(shù)： 18/38頁
文件大?。?/td> 435K
代理商： AK4396VF
ASAHI KASEI
[AK4396]
MS0336-E-00
2004/08
- 18 -
OPERATION OVERVIEW
D/A Conversion Mode
In serial mode, the AK4396 can perform D/A conversion for either PCM data or DSD data. The D/P bit controls
PCM/DSD mode. When DSD mode, DSD data can be input from DCLK, DSDL and DSDR pins. When PCM mode,
PCM data can be input from BICK, LRCK and SDATA pins. When PCM/DSD mode changes by D/P bit, the AK4396
should be reset by RSTN bit. It takes about 2/fs to 3/fs to change the mode. In parallel mode, the AK4396 performs for
only PCM data.
D/P bit
0
1
Table 1. PCM/DSD Mode Control
System Clock
[1] PCM Mode
The external clocks, which are required to operate the AK4396, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. When external clocks are changed, the AK4396 should be reset by PDN pin or RSTN bit.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4396 is in normal operation
mode (PDN pin = “H”). If these clocks are not provided, the AK4396 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4396 should be in the power-down mode
(PDN pin = “L”) or in the reset mode (RSTN bit = “0”). After exiting reset (PDN pin = “L”
→
“H”) at power-up etc., the
AK4396 is in power-down mode until MCLK is supplied.
(1) Parallel Mode (P/S pin = “H”)
1. Manual Setting Mode (ACKS pin = “L”)
MCLK frequency is detected automatically and the sampling speed is set by DFS0 pin (Table 2). The MCLK frequency
corresponding to each sampling speed should be provided (Table 3). DFS1 bit is fixed to “0”. When DFS0 pin is changed,
the AK4396 should be reset by PDN pin. Quad speed mode is not supported in this mode.
DFS0 pin
Sampling Rate (fs)
L
Normal Speed Mode
H
Double Speed Mode
Table 2. Sampling Speed (Manual Setting Mode @Parallel Mode)
LRCK
MCLK (MHz)
fs
128fs
192fs
256fs
384fs
32.0kHz
N/A
N/A
8.1920
12.2880
44.1kHz
N/A
N/A
11.2896
16.9344
48.0kHz
N/A
N/A
12.2880
18.4320
88.2kHz
11.2896
16.9344
22.5792
33.8688
96.0kHz
12.2880
18.4320
24.5760
36.8640
Table 3. System Clock Example (Manual Setting Mode @Parallel Mode)
Interface
PCM
DSD
30kHz
～
54kHz
54kHz
～
108kHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
5.6448MHz
6.1440MHz
512fs
16.3840
22.5792
24.5760
N/A
N/A
768fs
24.5760
33.8688
36.8640
N/A
N/A
1152fs
36.8640
N/A
N/A
N/A
N/A
相關(guān)PDF資料
PDF描述
AK4397 High Performance Premium 32-Bit DAC
AK4397EQ High Performance Premium 32-Bit DAC
AK4420 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output
AK4420ET 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output
AK4516A 3V 16bit ADC & DAC with built-in PGA(3V 16位帶內(nèi)置的模擬輸入可編程增益放大器的A/D轉(zhuǎn)換器和D/A轉(zhuǎn)換器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4396VFP-E2 功能描述:IC DAC 24BIT STEREO 28VSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF)
AK4397 制造商:AKM 制造商全稱:AKM 功能描述:192kHz sampling 32Bit ツヒ DAC
AK4397EQ 制造商:AKM 制造商全稱:AKM 功能描述:High Performance Premium 32-Bit DAC
AK4399 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 123dB Premium 32-Bit DAC
AK4399EQ 制造商:AKM 制造商全稱:AKM 功能描述:High Performance 123dB Premium 32-Bit DAC
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報(bào)價(jià)

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*