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參數(shù)資料
| 型號： | AK4370 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 24-Bit 2ch DAC with HP-AMP & Output Mixer |
| 中文描述： | 24位2通道DAC，具有惠普腺苷 |
| 文件頁數(shù)： | 31/49頁 |
| 文件大?。?/td> | 695K |
| 代理商： | AK4370 |
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ASAHI KASEI
[AK4370]
MS0595-E-00
2007/03
- 31 -
2) DAC
→
Lineout
Power Supply
PDN pin
PMVCM bit
Clock Input
(5)
SDTI pin
PMDAC bit
DAC Internal
State
PD(Power-down)
Normal Operation
PMLO bit
ATTL/R7-0 bits
00H(MUTE)
FFH(0dB)
LOUT/ROUT pins
(6)
LMUTE,
ATTS3-0 bits
10H(MUTE)
0FH(0dB)
(7) GD
(8) 1061/fs
(Hi-Z)
PD
Normal Operation
00H(MUTE)
FFH(0dB)
(Hi-Z)
(7) (8)
(6)
(6)
(7) (8)
Don’t care
Don’t care
Don’t care
(1) >150ns
(2)
>0s
(4) >0s
DALL,
DARR bits
(3) >0s
Figure 25. Power-up/down sequence of DAC and LOUT/ROUT (Don’t care: except Hi-Z)
(1)
When AVDD and DVDD are supplied separately, AVDD should be powered-up after DVDD rises up to 1.6V or
more. When AVDD and HVDD are supplied separately, AVDD should be powered-up at the same time or earlier
than HVDD. PDN pin should be set to “H” at least 150ns after power is supplied.
(2)
PMVCM bit should be changed to “1” after the PDN pin goes “H”.
(3)
DALL and DARR bits should be changed to “1” after the PMVCM bit is changed to “1”.
(4)
PMDAC and PMLO bits should be changed to “1” after DALL and DARR bits is changed to “1”.
(5)
External clocks (MCKI, BICK, LRCK) are needed to operate the DAC. When the PMDAC bit = “0”, these clocks
can be stopped. The LOUT/ROUT buffer can operate without these clocks.
(6)
When the PMLO bit is changed, pop noise is output from LOUT/ROUT pins.
(7)
Analog output corresponding to the digital input has a group delay (GD) of 22fs(=499
μ
s@fs=44.1kHz).
(8)
The ATS bit sets the transition time of the digital attenuator. Default value is 1061/fs(=24ms@fs=44.1kHz).
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