參數(shù)資料
型號: AK4370
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: 24-Bit 2ch DAC with HP-AMP & Output Mixer
中文描述: 24位2通道DAC,具有惠普腺苷
文件頁數(shù): 11/49頁
文件大?。?/td> 695K
代理商: AK4370
ASAHI KASEI
[AK4370]
MS0595-E-00
2007/03
- 11 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD, DVDD, HVDD=1.6
3.6V; C
L
= 20pF; unless otherwise specified)
Parameter
Master Clock Input Timing
Frequency
Pulse Width Low (Note 22)
Pulse Width High (Note 22)
AC Pulse Width (Note 23)
LRCK Timing
Frequency
Duty Cycle: Slave Mode
Master Mode
Serial Interface Timing
(Note 24)
Slave Mode (M/S bit = “0”):
BICK Period (Note 25)
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
” (Note 26)
BICK “
” to LRCK Edge (Note 26)
SDATA Hold Time
SDATA Setup Time
Master Mode (M/S bit = “1”):
BICK Frequency (BF bit = “1”)
(BF bit = “0”)
BICK Duty
BICK “
” to LRCK
SDATA Hold Time
SDATA Setup Time
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
” to CCLK “
CCLK “
” to CSN “
Note 22. Except AC coupling.
Note 23. Pulse width to ground level when MCKI is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 3.)
Note 24. Refer to “Serial Data Interface”.
Note 25. Min is longer value between 312.5ns or 1/(64fs) except for PLL Mode, PLL4-0 bits = “EH”, “FH”.
Note 26. BICK rising edge must not occur at the same time as LRCK edge.
Symbol
fCLK
tCLKL
tCLKH
tACW
fs
Duty
Duty
min
2.048
0.4/fCLK
0.4/fCLK
20.3
8
45
-
typ
-
-
-
-
44.1
-
50
max
24.576
-
-
-
48
55
-
Units
MHz
ns
ns
ns
kHz
%
%
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
fBCK
fBCK
dBCK
tMBLR
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
312.5 or 1/(64fs)
100
100
50
50
50
50
-
-
-
-
-
-
-
1/(32fs)
-
-
-
-
-
-
-
-
-
50
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
Hz
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
64fs
32fs
50
-
-
-
-
-
-
-
-
-
-
-
50
50
50
200
80
80
40
40
150
50
50
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