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參數(shù)資料
| 型號： | AK4366 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Low Power 24-Bit 2ch DAC with HP-AMP |
| 中文描述： | 低功耗24位2通道DAC，具有惠普腺苷 |
| 文件頁數(shù)： | 8/31頁 |
| 文件大小： | 266K |
| 代理商： | AK4366 |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4366]
REV 0.6
2003/3
- 8 -
DC CHARACTERISTICS
(Ta=25
°
C; VDD, HVDD=2.2
～
3.6V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
Input Voltage at AC Coupling
Input Leakage Current
Note 13. Only MCLK pin. (Figure 19)
Note 14. P/S pin has internal pull-down device, nominally 100k
.
Symbol
VIH
VIL
VAC
Iin
min
typ
-
-
-
-
max
-
Units
V
V
Vpp
μ
A
(Note 13)
(Note 14)
70
%
DVDD
-
0.4
-
30
%
DVDD
-
±
10
SWITCHING CHARACTERISTICS
(Ta=25
°
C; VDD, HVDD=2.2
～
3.6V; C
L
= 20pF)
Parameter
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
AC Pulse Width
LRCK Timing
Frequency
Duty Cycle:
Serial Interface Timing
(Note 16)
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑
”
BICK “
↑
” to LRCK Edge
SDATA Hold Time
SDATA Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
↑
” to CCLK “
↑
”
CCLK “
↑
” to CS “
↑
”
Note 15. Except AC coupling.
Note 16. Refer to “Serial Data Interface”.
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to ground.
(Refer to Figure 3.)
Symbol
fCLK
tCLKL
tCLKH
tACW
fs
Duty
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
min
2.048
0.4/fCLK
0.4/fCLK
20
8
45
1/(64fs)
130
130
50
50
50
50
200
80
80
40
40
150
50
50
typ
-
-
-
-
44.1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
24.576
-
-
-
48
55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
MHz
ns
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 15)
(Note 15)
(Note 18)
(Note 17)
(Note 17)
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