參數(shù)資料
型號(hào)： AK4366
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： Low Power 24-Bit 2ch DAC with HP-AMP
中文描述： 低功耗24位2通道DAC，具有惠普腺苷
文件頁(yè)數(shù)： 12/31頁(yè)
文件大小： 266K
代理商： AK4366
ASAHI KASEI
AKM CONFIDENTIAL
[AK4366]
REV 0.6
2003/3
- 12 -
OPERATION OVERVIEW
n
System Clock
The external clocks required to operate the AK4366 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter. The
frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency. Table 1
shows system clock example.
In serial mode (P/S= “L”), when the sampling frequency is changed during normal operation (PMDAC= “1”), the DAC
output should be soft-muted or “0” data should be input to avoid click noise.
In parallel mode (P/S= “H”), when the sampling frequency is changed during normal operation (PDN= “H”), the DAC
output should be soft-muted or “0” data should be input to avoid click noise.
LRCK
MCLK (MHz)
fs
256fs
384fs
8kHz
2.048
3.072
11.025kHz
2.8224
4.2336
12kHz
3.072
4.608
16kHz
4.096
6.144
22.05kHz
5.6448
8.4672
24kHz
6.144
9.216
32kHz
8.192
12.288
44.1kHz
11.2896
16.9344
48kHz
12.288
18.432
Table 1. System Clock Example
In serial mode (P/S= “L”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC is
in normal operation mode (PMDAC bit = “1”). If these clocks are not provided, the AK4366 may draw excess current and
will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are
not present, the DAC should be placed in power-down mode (PMDAC bit = “0”). When MCLK is input with AC coupling,
the MCKAC bit should be set to “1”.
In parallel mode (P/S= “H”), all external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC
is in normal operation mode (PDN pin = “H”). If these clocks are not provided, the AK4366 may draw excess current and
will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are
not present, the DAC should be placed in power-down mode (PDN pin = “L”).
For low sampling rates, DR and S/N degrade because of the outband noise. In serial mode (P/S= “L”), DR and S/N are
improved by setting DFS1 bit to “1”. Table 2 shows S/N of HP-amp output. When the DFS1 bit is “1”, MCLK needs 512fs.
Over Sample
Rate
0
0
64fs
8kHz
～
48kHz
256fs/384fs/512fs
0
1
128fs
8kHz
～
24kHz
256fs/384fs/512fs
1
x
256fs
8kHz
～
12kHz
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp
BICK (MHz)
64fs
0.512
0.7056
0.768
1.024
1.4112
1.536
2.048
2.8224
3.072
512fs
4.096
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
S/N (fs=8kHz, A-weighted)
HP-amp
56dB
75dB
92dB
Default
DFS1
DFS0
fs
MCLK
512fs
相關(guān)PDF資料
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