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參數(shù)資料
| 型號： | AK4366 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | Low Power 24-Bit 2ch DAC with HP-AMP |
| 中文描述： | 低功耗24位2通道DAC，具有惠普腺苷 |
| 文件頁數(shù)： | 18/31頁 |
| 文件大?。?/td> | 266K |
| 代理商： | AK4366 |
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ASAHI KASEI
AKM CONFIDENTIAL
[AK4366]
REV 0.6
2003/3
- 18 -
n
De-emphasis Filter
The AK4366 includes a digital de-emphasis filter (tc = 50/15
μ
s) by IIR filter corresponding to three sampling frequencies
(32kHz, 44.1kHz and 48kHz). In serial mode (P/S= “L”), the de-emphasis filter is enabled by setting DEM1-0 bits (Table
7).
DEM1 bit
DEM0 bit
0
0
0
1
1
0
1
1
Table 7. De-emphasis Filter Frequency Select (Serial Mode)
In parallel mode (P/S= “H”), the de-emphasis filter corresponding to 44.1kHz is enabled by setting DEM pin “H” (Table
8).
DEM pin
L
H
Table 8. De-emphasis Filter Frequency Select (Parallel Mode)
n
Bass Boost Function
In serial mode (P/S= “L”), the low frequency boost signal can be output from DAC by controlling BST1-0 bits (Table 9).
The setting value is common in Lch and Rch.
BST1 bit
BST0 bit
0
0
0
1
1
0
1
1
Table 9. Low Frequency Boost Select
n
System Reset
The AK4366 should be reset once by bringing PDN “L” upon power-up.
In serial mode (P/S= “L”), after exiting reset, VCOM, DAC, HPL and HPR switch to the power-down state. The contents
of the control register are maintained until the reset is done. DAC exits reset and power down state by MCLK after
PMDAC bit is changed to “1”, and then DAC is powered up and the internal timing starts clocking by LRCK “
↑
”. DAC is
in power-down mode until MCLK and LRCK are input.
In parallel mode (P/S= “H”), VCOM and DAC are powered up by PDN pin “H”. Headphone amp is powered up by
MUTEN pin “H”. DAC exits reset and power down state by MCLK after PDN pin goes to “H”, and then DAC is powered
up and the internal timing starts clocking by LRCK “
↑
”. DAC is in power-down mode until MCLK and LRCK are input.
De-emphasis
44.1kHz
OFF
48kHz
32kHz
Default
De-emphasis
OFF
44.1kHz
BOOST
OFF
MIN
MID
MAX
Default
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