參數(shù)資料
型號(hào)： AK4359VF
廠商： ASAHI KASEI POWER DEVICES CORP
元件分類： DAC
英文描述： 192 KHZ 24 BIT 8CH DAC
中文描述： SERIAL INPUT LOADING, 24-BIT DAC, PDSO30
封裝： LEAD FREE, PLASTIC, VSOP-30
文件頁(yè)數(shù)： 21/32頁(yè)
文件大小： 369K
代理商： AK4359VF
ASAHI KASEI
[AK4359]
MS0289-E-00
2004/02
- 21 -
Reset Function (RSTN bit)
When RSTN bit = “0”, internal circuit of DAC is powered down but the registers are not initialized. The analog outputs
go to VCOM voltage and DZF pins go to “H” at DZFB bit = “0”. Figure 13 shows the example of reset by RSTN bit. When
RSTN bit = “0”, pop noise is decreased at no clock state.
Internal
State
RSTN bit
Digital Block Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1)
(3)
DZF
(3)
(1)
(2)
Normal Operation
2/fs(5)
Internal
RSTN bit
2~3/fs (6)
3~4/fs (6)
Don’t care
(4)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Small pop noise occurs at the edges(“
↑
↓
”) of the internal timing of RSTN bit. This noise is output even if “0”
data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “0”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
Figure 13. Reset Sequence Example (DZFB bit = “0”)
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