參數(shù)資料
型號(hào)： AK4359VF
廠商： ASAHI KASEI POWER DEVICES CORP
元件分類： DAC
英文描述： 192 KHZ 24 BIT 8CH DAC
中文描述： SERIAL INPUT LOADING, 24-BIT DAC, PDSO30
封裝： LEAD FREE, PLASTIC, VSOP-30
文件頁(yè)數(shù)： 12/32頁(yè)
文件大小： 369K
代理商： AK4359VF
ASAHI KASEI
[AK4359]
MS0289-E-00
2004/02
- 12 -
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4359, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit
= “0”: Register 00H), the sampling speed is set by DFS0-1 (Table 1). The frequency of MCLK at each sampling speed is
set automatically. (Table 2~Table 4) In Auto Setting Mode (ACKS bit = “1”: Default), as MCLK frequency is detected
automatically (Table 5), and the internal master clock becomes the appropriate frequency (Table 6), it is not necessary to
set DFS0-1.
In parallel mode, the sampling speed can be set by only ACKS pin. Both DFS0 and DFS1 are fixed to “0”. When ACKS
pin = “L”, the AK4359 operates by Normal Speed Mode. When ACKS pin = “H”, Auto setting mode is enabled. The
parallel mode does not support 128fs and 192fs of Double Speed Mode.
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4359 is in the normal operation
mode (RSTB pin = ”H”). If these clocks are not provided, the AK4359 may draw excess current and may fall into
unpredictable operation. This is because the device utilizes dynamic refreshed logic internally. The AK4359 should be
reset by RSTB pin = “L” after threse clocks are provided. If the external clocks are not present, the AK4359 should be in
the power-down mode (RSTB pin = ”L”). After exiting reset(RSTB = “
↑
”) at power-up etc., the AK4359 is in the
power-down mode until MCLK is input.
DFS1
DFS0
0
0
Normal Speed Mode
0
1
Double Speed Mode
1
0
Quad Speed Mode
Sampling Rate (fs)
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
MCLK
512fs
16.3840MHz
22.5792MHz
24.5760MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
256fs
384fs
768fs
1152fs
36.8640MHz
N/A
N/A
8.1920MHz 12.2880MHz
11.2896MHz 16.9344MHz
12.2880MHz 18.4320MHz
24.5760MHz
33.8688MHz
36.8640MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
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