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參數(shù)資料
| 型號(hào)： | AK4359VF |
| 廠商： | ASAHI KASEI POWER DEVICES CORP |
| 元件分類： | DAC |
| 英文描述： | 192 KHZ 24 BIT 8CH DAC |
| 中文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PDSO30 |
| 封裝： | LEAD FREE, PLASTIC, VSOP-30 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 369K |
| 代理商： | AK4359VF |
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ASAHI KASEI
[AK4359]
MS0289-E-00
2004/02
- 20 -
System Reset
The AK4359 should be reset once by bringing RSTB pin = ”L” upon power-up. The analog section exits power-down
mode by MCLK input and then the digital section exits power-down mode after the internal counter counts MCLK during
4/fs.
Power ON/OFF timing
All DACs are placed in the power-down mode by bringing RSTB pin “L” and the registers are initialized. the analog
outputs go to Hi-Z. As some click noise occurs at the edge of RSTB signal, the analog output should be muted externally
if the click noise influences system application.
Each DAC can be powered down by setting each power-down bit (PW1-4) to “0”. In this case, the registers are not
initialized and the corresponding analog outputs go to VCOM. As some click noise occurs at the edge of RSTB signal, the
analog output should be muted externally if the click noise influences system application.
RSTB pin
Power
Reset
Normal Operation
Clock In
MCLK,LRCK,SCLK
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(5)
DZF1/DZF2
Don’t care
“0”data
GD
(1)
(3)
(4)
(6)
GD
(3)
Mute ON
“0”data
Don’t care
Internal
State
(2)
(2)
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are floating (Hi -Z) at the power-down mode.
(3) Click noise occurs at the edge of RSTB signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTB pin = “L”).
(5) Please mute the analog output externally if the click noise (3) influence system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (RSTB pin = “L”). (DZFB bit = “0”)
Figure 12. Power-down/up Sequence Example
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