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參數(shù)資料
| 型號： | AK4340_06 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output |
| 中文描述： | 192kHz的24位立體聲ツヒDAC，具有2Vrms的輸出 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大小： | 259K |
| 代理商： | AK4340_06 |
ASAHI KASEI
[AK4340]
MS0501-E-00
2006/04
- 17 -
Mode Control Interface
Some function of the AK4340 can be controlled by pins (parallel control mode) shown in Table 11. The serial control
interface is enabled by the P/S pin = “L”. Internal registers may be written to 3-wire μP interface pins, CSN, CCLK and
CDTI. The data on this interface consists of Chip Address (2bits, C1/0; fixed to “01”), Read/Write (1bit; fixed to “1”,
Write only), Register Address (MSB first, 5bits) and Control Data (MSB first, 8bits). The AK4340 latches the data on the
rising edge of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by CSN “
↑
”. The
clock speed of CCLK is 5MHz (max).
Function
Parallel control mode
Double sampling mode at 128/192fs
De-emphasis
SMUTE
16/20/24bit LSB justified format
Table 11. Function list (O: available, X: not available)
PDN pin = “L” resets the registers to their default values. When the state of P/S pin is changed, the AK4340 should be
reset by PDN pin = “L”. The internal timing circuit is reset by RSTN bit, but the registers are not initialized.
Serial control mode
O
O
O
O
X
X
O
X
CDTI
CCLK
C1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D4
D5
D6
D7
A1
A2
A3
A4
R/W
C0
A0
D0
D1
D2
D3
CSN
C1-C0: Chip Address (Fixed to “01”)
R/W: READ/WRITE (Fixed to “1”, Write only)
A4-A0: Register Address
D7-D0: Control Data
Figure 14. Control I/F Timing
*The AK4340 does not support the read command and chip address. C1/0 and R/W are fixed to “011”
*When the AK4340 is in the power down mode (PDN pin = “L”) or the MCLK is not provided, writing into the control
register is inhibited.
Register Map
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
00H
01H
02H
03H
04H
Notes:
Control 1
Control 2
Control 3
Lch ATT
Rch ATT
ACKS
0
0
ATT7
ATT7
0
0
0
0
0
0
DIF2
DFS1
INVL
ATT4
ATT4
DIF1
DFS0
INVR
ATT3
ATT3
DIF0
DEM1
0
ATT2
ATT2
PW
DEM0
0
ATT1
ATT1
RSTN
SMUTE
0
ATT0
ATT0
ATT6
ATT6
ATT5
ATT5
For addresses from 05H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the only internal timing is reset and the registers are not initialized to their default
values. All data can be written to the register even if PW or RSTN bit is “0”.
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