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參數(shù)資料
| 型號： | AK4340_06 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 192kHz 24-Bit Stereo ツヒ DAC with 2Vrms Output |
| 中文描述： | 192kHz的24位立體聲ツヒDAC，具有2Vrms的輸出 |
| 文件頁數(shù)： | 16/23頁 |
| 文件大?。?/td> | 259K |
| 代理商： | AK4340_06 |
ASAHI KASEI
[AK4340]
MS0501-E-00
2006/04
- 16 -
Reset Function
When RSTN=0, DAC is powered down but the internal register values are not initialized. The analog outputs go to
VCOM voltage and DZF pin goes to “H”. Figure 7 shows the example of reset by RSTN bit.
RSTN bit
Internal
State
Digital Block Power-down
Normal Operation
GD
GD
“0” data
D/A Out
(Analog)
D/A In
(Digital)
Clock In
MCLK,LRCK,BICK
(1)
(3)
External
MUTE
(3)
(1)
(2)
Normal Operation
Internal
RSTN bit
2~3/fs (6)
3~4/fs (6)
Don’t care
(4)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage (VDD/2).
(3) Click noise occurs at the edges(“
↑
↓
”) of the internal timing of RSTN bit. This noise is output even if “0” data is
input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN = “L”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN “1”.
Figure 13. Reset Sequence Example
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