參數(shù)資料
型號: AK4121
廠商: Asahi Kasei Microsystems Co.,Ltd
英文描述: ASYNCHRONOUS SAMPLE RATE CONVERTER
中文描述: 異步采樣率轉(zhuǎn)換器
文件頁數(shù): 14/19頁
文件大?。?/td> 196K
代理商: AK4121
ASAHI KASEI
[AK4121]
MS0191-E-03
2004/08
- 14 -
Grounding and Power Supply Decoupling
The AK4121 requires careful attention to power supply and grounding arrangements. VDD are usually supplied from
the system’s analog supply.
AVSS and DVSS of the AK4121 must be connected to the analog ground plane.
System analog ground and digital ground should be connected together near to where the supplies are brought onto the
printed circuit board. Decoupling capacitors especially a 0.1
μ
F ceramic capacitor for high frequency noise should be
placed as near to VDD as possible.
PLL Loop-Filter
The C1 (4.7
μ
F) and R (560ohms) should be connected in series and attached between FILT pin and AVSS in parallel
with C2 (1.0nF). Care should be taken to ensure that noise on the FILT pin is minimized.
FILT
AK4121
C1
R
AVSS
C2
Parameter
R
C1
C2
fsi range
Recommended value 1
560ohm +/
8%
4.7
μ
F +/
40%
1.0nF +/
40%
8k ~ 96kHz
Note: Those recommended values include temperature dependence.
Recommended value 2
1.2kohm +/
8%
2.2
μ
F +/
40%
2.2nF +/
40%
16k ~ 96kHz
Figure 7. PLL Loop-Filter
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