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參數(shù)資料
| 型號： | AK4121 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | ASYNCHRONOUS SAMPLE RATE CONVERTER |
| 中文描述： | 異步采樣率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/19頁 |
| 文件大?。?/td> | 196K |
| 代理商： | AK4121 |
ASAHI KASEI
[AK4121]
MS0191-E-03
2004/08
- 13 -
Internal Reset Function for Clock Change
The internal reset is executed when the input or the output clock are changed. The SDTO is placed “0” during reset.
Within 100ms, the SDTO outputs normal data. When the frequency transition occurs gradually without phase change or
the clock of output port is changed keeping fso/fsi > 4, the internal reset is not executed and the SDTO takes time over
100ms to output normal data. To output normal data within 100ms, please reset by PDN=“L”(refer following section).
Sequence of changing clocks
The recommended sequence for changing clocks is shown in Figure 6.
External clocks
(input port
or output port)
< 10msec
PLL locktime
& fs detection
Power
down
state 1
SDTO
(interlal state)
normal operation
normal operation
state 2
(unknown)
< 100msec
SMUTE (Note2,
recommended)
1024/fso
Att.Level
0dB
-
∞
dB
normal data
normal data
1024/fso
PDN
Note1
Figure 6. Sequence of changing clocks
Note:
1. The data on SDTO may cause a clicking noise. To prevent this, set SDTI to “0” from GD before PDN goes
“L”, which will cause the data on SDTO to remain “0”.
2. SMUTE can also be used to remove the unknown data.
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