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參數(shù)資料
| 型號(hào)： | AK4121 |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | ASYNCHRONOUS SAMPLE RATE CONVERTER |
| 中文描述： | 異步采樣率轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 196K |
| 代理商： | AK4121 |
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ASAHI KASEI
[AK4121]
MS0191-E-03
2004/08
- 12 -
System Reset
Bringing the PDN=“L” places the AK4121 in power-down mode and initializes the digital filter. The AK4121 should
be reset once by bringing PDN=“L” upon power-up. Regarding the SDTO valid time, please refer following table. Until
then, the SDTO outputs “L”.
Case 1
Case 2
External clocks
(output port)
t
a
External clocks
(input port)
SDTI
don’t care
SDTO
(internal state)
Power-down
normal
operation
PLL lock &
fs detection
t
b
normal data
(state1)
External clocks
(output port)
don’t care
don’t care
PDN
Power-down
don’t care
don’t care
don’t care
“0” data
normal
operation
PLL lock &
fs detection
(note)
normal data
PD
(state1)
(state1)
(state2)
(state2)
(state2)
“0” data
“0” data
External clocks
(input port)
SDTI
SDTO
(internal state)
Power-down
normal
operation
PLL lock &
fs detection
(note)
normal data
(no clock)
PDN
Power-down
don’t care
don’t care
don’t care
“0” data
PLL
Unlock
(state1)
(state1)
(state1)
“0” data
(don’t care)
(don’t care)
Note: <100ms for recommended value 2, <200ms for recommended value 1. (ref. Figure 7)
Figure 5. System Reset
Reset time
t
a
≤
10ms
10ms<
Table 5. Reset time t
a
and Data valid time t
b.
Data valid time
t
b
<100ms
<200ms
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