參數(shù)資料
型號(hào)： AHA4011C-040PJC
廠商： Electronic Theatre Controls, Inc.
英文描述： 10 MBytes/sec Reed-Solomon Error Correction Device
中文描述： 10兆字節(jié)/秒的Reed - Solomon糾錯(cuò)裝置
文件頁(yè)數(shù)： 7/28頁(yè)
文件大?。?/td> 466K
代理商： AHA4011C-040PJC
PS4011C-0200
Page 3 of 24
Advanced Hardware Architectures, Inc.
The use of internal buffers is restricted per the
rules defined in Section 2.9
Data Rates and
Latencies
.
Maximum delay required for each block of a
given length to pass through the device is fixed, and
does not vary with the location or the number of
errors received. This delay (or latency), expressed
in the number of clocks is discussed in a later
section.
2.2
CORRECTING CAPABILITY AND
POLYNOMIALS
Compared with other codes, RS codes require
relatively few “overhead” check bytes to be added
to the data stream to achieve a high degree of error
detection and correction. Since the AHA4011C
deals with bytes (or symbols) rather than with
individual bits, when a byte is in error it does not
matter how many bits within the byte are corrupted;
it is counted as one error.
The Reed-Solomon code is defined over the
finite field GF(2
8
). The field defining primitive
polynomial is:
P(x) = x
8
+ x
7
+ x
2
+ x + 1
and the generator polynomial, dependent on the
variable R, is given by:
119
=
where R
∈
{2, 3, 4, 5,. . . 20} for the AHA4011C.
This polynomial is specified in international
standards, Intelsat IESS 308; RTCA DO-217
Appendix F (Rev D) and the proposed CCITT
SG-18.
For every 2 check bytes, the decoder corrects
either 2 erasures or 1 error. An erasure can be
determined with a parity detector or a signal dropout
detector external to the chip. An erasure is indicated
by the ERASE signal when the erased byte is
clocked in the device.
Correcting “erasures” takes only half as much
of the correction capability of the RS code as it takes
to correct “errors”, since the position information is
already known for “erasures”. The correction ability
of the code is bounded as:
R
≥
# erasures
+
2(# errors)
Valid block length (N) is defined by the
relationship:
R + 1
≤
N
≤
255
where R ranges from 2 to 20.
A complete codeword can therefore range from
a minimum of 3 bytes to a maximum of 255 bytes.
For further discussion on error rate
performance, refer to Section 2.1
Reed-Solomon
(ECC) Module and Error Rate Performance
.
Figure 1:
Block Diagram
A typical system block diagram is shown in the
following figure.
Figure 2:
Typical Applications Diagram
G x
( )
x
α
i
–
(
)
i
120
=
R
+
∏
DI
INPUT BUFFER
367x9
ECC CORE
CONTROL
DO
OUTPUT BUFFER
256x9
REGISTER
RDYON
RSTN
DSIN
DSON
GND
VDD
CRTN
RDYIN
CLK
RDYIN
REGISTER
ERASE DI[7:0]
CLK
RSTN
DSIN
DSON
RDYON
CRTN
DO[7:0] ERR
VDD
GND
DATA SOURCE
AHA4011C
ECC COPROCESSOR
CHANNEL
1 TO x BITS WIDE
AHA4011C
ECC COPROCESSOR
DATA SINK
SYSTEM
CONTROLLER
SYSTEM
CONTROLLER
A
8
8
8
8
B
C
ENCODER
COMMUNICATIONS
DECODER
BLOCK FORMAT AT:
KDATA PLUS R “DUMMY” BYTES
KDATA PLUS R CHECK BYTES
KDATA BYTES
C
A
B
相關(guān)PDF資料
PDF描述
AHA4011C EMC® STANDOFF TERMINAL
AHA4013B 12.5 MBytes/sec Reed-Solomon Error Correction Device
AHA4013B-050PJC 12.5 MBytes/sec Reed-Solomon Error Correction Device
AHA4541 311 MBITS/SEC TURBO PRODUCT CODE ENCODER/DECODER
AHA4541A-PQC 311 MBITS/SEC TURBO PRODUCT CODE ENCODER/DECODER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AHA4012A-006/PJC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Error Detection & Correction (EDAC)
AHA4012B 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:1.5 MBytes/sec Reed-Solomon Error Correction Device
AHA4012B-006 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:1.5 MBytes/sec Reed-Solomon Error Correction Device
AHA4012B-006PJC 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:1.5 MBytes/sec Reed-Solomon Error Correction Device
AHA4012B-006PJI 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:1.5 MBytes/sec Reed-Solomon Error Correction Device
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*