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參數(shù)資料
| 型號： | AHA4011C-040PJC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 MBytes/sec Reed-Solomon Error Correction Device |
| 中文描述： | 10兆字節(jié)/秒的Reed - Solomon糾錯裝置 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大?。?/td> | 466K |
| 代理商： | AHA4011C-040PJC |
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PS4011C-0200
Page 9 of 24
Advanced Hardware Architectures, Inc.
2.9.1
BURST OPERATION
Maximum processing latency, in forward order,
expressed in number of clocks, for burst operation is
determined by: N × C
i
+
R
+
60
+
N
Definitions:
C
i
=
input clock rate per byte. If C
i
= 1, use a value
for C
i
of 2 in the latency equation
N
=
block length
R
=
number of check bytes
Processing Latency
=
Delay from first input byte to
first output byte
In reverse order, processing latency is
approximately N clocks less than above.
For a 40 MHz system using 1 clock per byte,
latencies and data rates for forward order output are
shown in the table for burst operation. Input and
Output Burst Rates in all cases will be 40
MBytes/sec. Note: Other frequency operations may
be derived similarly.
Output Buffer may be used to hold data from
one block while the Input Buffer is being filled with
the following block. Two rules listed in the caveats
are required to accomplish this. These are illustrated
in Figure 4.
Caveats:
1. Output of block i must start coincident
with or before the input of block i
+
1.
2. Output of block i must be complete:
Processing Latency
N
8 clocks
after the start of block i
+
l on the input.
Table 2:
Burst Operation Using 40 MHz Clock and 1 Clock/Byte, Forward Order Output
2.0.1
CONTINUOUS OPERATION
Multiple blocks of data may be processed
through the device continuously as shown in Figure
4. Consecutive blocks are input into the device at
the rate of C
i
clocks/byte. The output data stream
may or may not be continuous depending on
whether parity is being output (controlled by
NOPAR) and the choice of C
o
. Continuous
operation is described by several equations. The
following terms are used in these equations:
C
i
-
Input clock rate per byte: C
i
≥
4 for
continuous operation
C
o
-
Output clock rate per byte: C
o
≥
2
C
m
-
Minimum of C
i
and C
o
: If C
i
< C
o
then
C
m
=
C
i
else C
m
=
C
o
N
-
Reed-Solomon block length
K
-
Reed-Solomon message length
R
-
Reed-Solomon parity length (R
=
N
K)
L
-
Output data length: If parity is being output
from the chip (NOPAR
=
0), L
=
N; else if
the parity is not being output (NOPAR
=
1)
L
=
K
A. Conditions for Continuous Operation
The allowable input and output data rates are
related to the Reed-Solomon block length by the
following two inequalities. C
i
, C
o
, N and K must be
chosen so that these equations are satisfied.
Equation 1:
R
60
C
–
C
i
Equation 2:
B. Processing Latency
Processing latency is the time from the
beginning of a block on the input to the block being
ready for output. Maximum processing latency,
expressed in number of clocks, for continuous
operation is:
Equation 3:
CHECK BYTES ‘R’ = 20
MAXIMUM
LATENCY
(# of clocks)
155
230
380
530
680
845
CHECK BYTES ‘R’ = 2
MAXIMUM
LATENCY
(# of clocks)
137
212
362
512
662
827
BLOCK
LENGTHS ‘N’
MAXIMUM
LATENCY
(
μ
secs)
3.88
5.75
9.50
13.30
17.00
21.10
AVERAGE
RATE
(MBytes/sec)
6.45
8.70
10.50
11.30
11.80
12.10
MAXIMUM
LATENCY
(
μ
secs)
3.43
5.30
9.05
12.80
16.60
20.70
AVERAGE
RATE
(MBytes/sec)
7.30
9.43
11.00
11.70
12.10
12.30
25
50
100
150
200
255
Average Rate
Maximum Latency
μ
sec
(
)
----------------------------N
=
-----------------
m
1
+
+
----------------------------------------
N
367
≤
+
N
1
–
(
)
C
i
×
R
48
N
C
i
i
1
–
---------------
N
C
m
m
–
1
-----------------
+
+
+
≥
Latency
N
1
–
(
)
C
i
×
=
60
R
N
C
m
m
–
1
-----------------
+
+
+
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|---|---|
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