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參數(shù)資料
| 型號： | AHA4011C-040PJC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 10 MBytes/sec Reed-Solomon Error Correction Device |
| 中文描述： | 10兆字節(jié)/秒的Reed - Solomon糾錯(cuò)裝置 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 466K |
| 代理商： | AHA4011C-040PJC |
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Page 10 of 24
PS4011C-0200
Advanced Hardware Architectures, Inc.
C. Start and End of Output
Similar to the burst operation, Output Buffer
may be used to temporarily “hold” data from one
block while the Input Buffer is being filled.
However, these conditions must be satisfied: the
output of a data block must start after the latency
equation (Equation 3) is satisfied, but before the
maximum delay is reached. The maximum delay is:
Equation 4:
Data of one block must be fully emptied L × C
o
clocks after the start of empty process.
All of the conditions on the maximum delay
given in Equation 4 must be satisfied. If any are not,
the output data stream will begin to inhibit ECC
processing. Eventually this will cause the input
buffer to over fill and RDYIN to become inactive.
Figure 4:
(Note: Blocks are shown from right to left as they are input into and output from the chip in Forward Order.
Block i is the first input block, block i + 1 is second input block. X
K
1
is the first input message byte of a block.
Y
o
is the last input check symbol of a block. Notes 1 and 2 in burst operation are described in Section 2.9.1 Burst
Operation - Caveats.)
Burst Operation
Burst and Continuous Operations
For a 40 MHz system using the required clocks per byte, maximum latencies and data rates for forward
order output are shown in the table for continuous operation. Input and Output rates are assumed the same
in this table. Note: Other frequency operations are also possible.
Table 3:
Continuous Operation Using 40 MHz Clock and Specified Clocks/Byte, Forward
Output Order
CHECK BYTES ‘R’ = 20
MINIMUM
REQUIRED
(clocks/byte)
(MBytes/sec)
(
μ
secs)
25
6
6.67
6.35
50
5
8
9.69
100
4
10
15.23
150
4
10
21.90
200
4
10
28.57
225
4
10
31.90
255
4
10
35.90
For Intelsat IESS-308, Rev F, Inner FEC Rates, use Table 4 for a system with 40 MHz clock.
Note: Other frequency operations are also possible.
maximum_delay
3
N
C
i
×
×
L
C
o
N
C
i
i
1
–
---------------
–
×
–
=
i
C
i
if maximum_delay
367, then maximum_delay
367
C
i
×
=
≥
if maximum_delay
2
N
, then maximum_delay
×
2
N
C
i
×
×
=
>
CHECK BYTES ‘R’ = 2
MINIMUM
REQUIRED
(clocks/byte)
(MBytes/sec)
5
5
4
4
4
4
4
BLOCK
LENGTHS ‘N’
MAXIMUM
DATA RATE
MAXIMUM
LATENCY
MAXIMUM
DATA RATE
MAXIMUM
LATENCY
(
μ
secs)
5.33
9.24
14.78
21.45
28.12
31.45
35.45
8
8
10
10
10
10
10
Input Data:
Output Data:
Block i+3
. . . . . . . . . .
Block i+2
. . . . . . . . . .
Block i+1
. . . . . . . . . .
Block i
. . . . . . . . . .
Y
0
Y
0
Y
0
Y
0
Block i+3
. . . . . . . . . .
Block i+2
. . . . . . . . . .
Block i+1
. . . . . . . . . .
Block i
. . . . . . . . . .
Y
0
Y
0
Y
0
Y
0
K-1
X
K-1
X
K-1
X
K-1
X
K-1
X
K-1
X
K-1
X
K-1
X
Continuous Operation
Block i
Block i+1
. . . . . . . . . .
Input Data:
Output Data:
Processing Latency
Block i+1
. . . . . . . . . .
Block i
. . . . . . . . . . . . . . . . . .
. . . . . . . . . .
Y
0
Y
0
Y
0
K-1
X
Y
0
K-1
X
K-1
X
K-1
X
2
1
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